Cadence Design Systems,
Inc. (NASDAQ: CDNS), the leader in global electronic design innovation,
today announced first-silicon results on 32-nanometer (nm) Common Platform high-k
metal-gate (HKMG) technology, manufactured at IBM. Cadence® and the Common
Platform alliance, comprised of IBM, Chartered Semiconductor Manufacturing and
Samsung Electronics, collaborated to tackle systematic and random variability
in advanced node designs. The silicon results represent a significant milestone
for designers with stringent design-for-manufacturing (DFM) requirements, and
can enable Encounter® Digital Implementation (EDI) System to provide significant
power savings, yield enhancement and time-to-market advantages.
The 32nm silicon results provide a rich and expansive data set modeling the
HKMG process in relation to layout rules, design rule checking and device interconnect
models. In addition, they capture critical information related to device and
interconnect variability, including systematic, random, within-die and die-to-die
variation, as well as manufacturing effects including lithography, thermal,
stress, proximity effects, and copper deposition. Using this manufacturing intelligence
during the physical design process, the Cadence Encounter Digital Implementation
System can enable early and silicon-accurate DFM and variability modeling, characterization
and optimization to provide a complete end-to-end flow.
"We've worked closely with Cadence to build early hardware for the purpose
of accurately modeling device and interconnect variability," said Mark
Ireland, vice president, IBM Semiconductor Platforms on behalf of the Common
Platform alliance. "The early learning will enable Cadence to incorporate
silicon-accurate models and DFM support into the Encounter tool suite. This
helps accelerate the adoption of 32/28nm high-k metal-gate technology for designers
to deliver next-generation devices with significantly improved performance and
battery life."
The EDI System contains a full suite of DFM and statistical technologies that
can be applied across the physical implementation flow. Manufacturing and yield
can be addressed concurrently with timing, signal integrity, power, and area
optimizations to ensure all aspects are addressed holistically before final
tapeout. By modeling and optimizing for variability early in the design stage,
designers reduce overall turnaround time and improve confidence that the chip
will work as intended. Once these technologies are validated on 32/28nm technology,
there is a potential to increase design predictability, resulting in higher-quality
silicon with better time to volume.
"With this announcement, Cadence demonstrates industry leadership with
innovative manufacturing partnerships," said Chi-Ping Hsu, senior vice
president of Research and Development for the Implementation Products Group
at Cadence. "The Cadence and Common Platform alliance collaboration on
32/28nm is yet another testimony to our long-term investment and commitment
to advanced technology development. Cadence continues its quickened pace of
product and technology leadership to help our customers bring their leading-edge
products first to market."