Site Sponsors
  • Strem Chemicals - Nanomaterials for R&D
  • Oxford Instruments Nanoanalysis - X-Max Large Area Analytical EDS SDD
  • Park Systems - Manufacturer of a complete range of AFM solutions

Cadence Delivers Performance and Integration for High-End SoC Designs Implemented in Advanced TSMC Processes

Published on September 29, 2009 at 7:46 PM

Cadence Design Systems, Inc. (NASDAQ: CDNS), the leader in global electronic design innovation, announced today that the Cadence Physical Verification System has adopted the new interoperable physical verification formats for 40-nanometer designs, consisting of iDRC for design rule checking and iLVS for layout vs. schematic checking, developed by Taiwan Semiconductor Manufacturing Company (TSMC). Cadence support of these new TSMC formats builds upon the previously announced Cadence QRC Parasitic Extraction support for the iRCX file format. This combination of physical verification and parasitic extraction and analysis capabilities ensures the continued availability of accurate and consistent manufacturing data to enhance silicon yield for Cadence customers using TSMC nanometer processes.

The iDRC and iLVS formats facilitate the advanced design rule and device extraction capabilities necessary to ensure the integrity of designs implemented in TSMC’s advanced processes. Using a common rule format ensures accuracy and consistent presentation of results regardless of the physical verification solution that each customer chooses.

“Cadence and TSMC have collaborated on iDRC, iLVS and iRCX to ensure that users of the Cadence Physical Verification System and QRC Parasitic Extraction have timely access to silicon-accurate checks for today’s nanometer processes, and the process generations beyond,” said Tom Quan, deputy director of design service marketing at TSMC. “The new unified data formats are part of the TSMC Open Innovation Platform™ that provides designers the ability to select best-in-class EDA tools to match their design needs and improve design accuracy for first time silicon success.”

“Adopting the new TSMC iDRC and iLVS rule deck formats takes the advanced capabilities of the Cadence Physical Verification System closer to the source of the process data,” said Dr. Rachid Salik, vice president of research and development for the verification group at Cadence. “This combination ensures that we can deliver accurate results with a rapid turnaround time. We are confident that the continued strengthening of our relationship with TSMC will bring real benefits, value, and choice to our mutual customers.”

The addition of iDRC and iLVS support in the Cadence Physical Verification System, and iRCX support in Cadence QRC extraction technology, provides complete integration with Cadence digital and custom design flows, and therefore providing a front-to-back design and signoff flow from a single EDA vendor. The product facilitates a “one tool, one deck” model for digital and custom design that minimizes support overhead.

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Submit