Cadence Design Systems, Inc. (NASDAQ:CDNS) , the leader in global electronic
design innovation, today announced that Semiconductor
Manufacturing International Corporation ("SMIC"; NYSE: SMI and SEHK:
0981.HK) has adopted Cadence(R) Litho Physical Analyzer and Cadence Litho
Electrical Analyzer to more accurately predict the impact of stress and lithographic
variability on the performance of 65- and 45-nanometer semiconductor designs.
The Cadence Litho Electrical Analyzer -- the semiconductor industry's first
electrical DFM solution in production at leading semiconductor companies from
90 nanometers to 40 nanometers -- combined with Cadence Litho Physical Analyzer
to create a flow that accurately predicted final silicon results.
Previously, the electrical behavior of individual cells and libraries could
be pre-characterized in a single context that could be consistently applied
to a given design based on the targeted process technology. At 65 nanometers
and below, each placement of a cell creates its own set of physical and electrical
variabilities relative to its neighboring cells or surroundings. This "context
dependent variability" is emerging as a critical issue, which can cause
the chip to fail. Cadence Encounter(R) Digital Implementation System (EDI) System
seamlessly integrates both the Litho Physical Analyzer and Litho Electrical
Analyzer for rigorous context-dependent physical and electrical signoff of cells
prior to full chip implementation. The flow leverages model- based physical
and electrical design for manufacturing (DFM) technologies to improve the quality
and reliability of standard cell libraries, intellectual property (IP) cores,
and full chip to increase manufacturing yield in full chips.
"The necessity to address physical and electrical variation at 65 and 45
nanometers requires a holistic approach that starts at the cell level and considers
the entire context of the design," said Max Liu, VP of SMIC Design Services
Center. "With the Cadence DFM flow, we could analyze cell and IP variability
and accurately model their performance in real silicon. By characterizing and
reducing the variability, our customers will be able to reduce guard-banding
and to produce higher quality silicon. The solution also enables near-linear
scalability, which is necessary for a full-chip electrical DFM verification
flow."
Cadence has developed one of the industry's most complete design side DFM prevention,
analysis, and signoff methodologies, including design-side optimizations with
Encounter Digital Implementation System. It is also being used for variability
modeling of 32- and 28-nanometer libraries. "Fast, accurate context-dependent
variability modeling of cells for both lithography and stress effects is key
to implementing production-worthy designs at 65 nanometers and below,"
said Dr. Chi-Ping Hsu, senior vice president of research and development for
the Implementation Group at Cadence. "Numerous first silicon successes
have already proven the value of DFM analysis tools for high-volume semiconductor
designs."