Cadence Design Systems,
Inc. (NASDAQ: CDNS), the leader in global electronic design innovation,
today announced that it has delivered a comprehensive low-power design flow
for engineers targeting the 65-nanometer process at Semiconductor Manufacturing
International Corporation ("SMIC") (NYSE: SMI) (SEHK: 0981.HK). Based
on the Cadence® Low-Power Solution, the flow enables faster design of leading-edge,
low-power semiconductors using a single, comprehensive design platform.
"Power is now a critical design constraint, as important as timing and
area from both a technology and cost standpoint," said Max Liu, vice president
of the Design Services Center at SMIC. "The SMIC-Cadence Reference Flow
4.0 addresses the need for power-efficient design innovation with an advanced,
automated low-power design capability."
Validation of the flow was accomplished through implementation of low-power
chips utilizing SMIC's in-house-designed 65-nanometer libraries, including effective
current source model (ECSM) standard cells, power management cells, PLLs, SRAMs
and I/O libraries. Low-power technologies employed in the design include power
gating and multi-supply/multi-voltage (MSMV) techniques to reduce leakage and
dynamic power consumption.
"Power efficiency is a key requirement for many new semiconductors, yet
designers sometimes think it's too new and therefore too risky," said Steve
Carlson, vice president of product marketing at Cadence. "The Cadence Low-Power
Solution provides a complete, silicon-validated front-to-back flow for designers
targeting SMIC's 65-nanometer process technology, including functional and structural
verification, while increasing productivity. It's fast, easy and proven."
The SMIC 65-nanometer low-power Reference Flow 4.0 includes the Cadence Low-Power
Solution, with Encounter® Conformal® Low Power, Incisive® Enterprise
Simulator, Encounter RTL Compiler, Encounter Digital Implementation System,
Cadence QRC Extraction, Encounter Timing System and Encounter Power System.