Magma® Design Automation Inc. (Nasdaq:LAVA), a provider of chip design software, today announced that Magma's Talus® and Quartz™ integrated circuit (IC) implementation and physical verification solutions have been included to support the TSMC Reference Flow 11.0. Through TSMC's Open Innovation Platform (OIP), Magma's product suite provides users with new 28-nanometer (nm) design methodology features to address the challenges of low power, performance and design for manufacturability (DFM).
"Magma has worked very closely with TSMC and a number of key customers targeting 28-nm silicon to address the new design challenges presented at that process technology node," said Premal Buch, general manager of Magma's Design Implementation Business Unit. "As a result of this collaborative effort, our customers have already begun successfully taping out test chips targeted for TSMC's 28-nm process. The combination of the Talus and Quartz solutions and TSMC's Reference Flow 11.0 provides faster timing closure on large, tough designs without sacrificing performance or increasing power consumption."
"Our collaboration with Magma and several of our mutual customers has resulted in significant improvements in the manufacturability of nanometer designs," said S.T. Juang, senior director of design infrastructure marketing at TSMC. "Magma's Talus and Quartz have been validated for Reference Flow 11.0 to support TSMC's 28-nm process node, which will benefit our mutual leading-edge customers."
28-nm Design Enablement
Magma's Talus RTL-to-GDSII IC Implementation system supports TSMC 28-nm design rules that have been enhanced in Reference Flow 11.0. Talus' support of Reference Flow 11.0 takes advantage of new power, performance and DFM features, providing customers with faster overall design closure and better performance and predictability. In addition, Magma's Quartz DRC and Quartz LVS physical verification tools support sign-off and in-the-loop physical verification. Quartz DRC and Quartz LVS are official components of TSMC's 65nm Integrated Sign-Off (ISF) Flow and runsets are available from TSMC OnlineSM.
At 28 nm and below it becomes increasingly complicated to capture the number of potential variations at all process corners. With Reference Flow 11.0, greater performance is achieved using multiple advanced stage-based on-chip variation (OCV) optimization and analysis tables instead of a single advanced OCV table. This analysis technique is available in Tekton™, Magma's new standalone static timing analysis tool, and is also supported by Talus Vortex. This technique can reduce OCV timing margins and improve performance by removing some of the pessimism associated with traditional OCV.
New Low-Power Features
TSMC extends its support for both the Common Power Format (CPF) and Unified Power Format (UPF) in Reference Flow 11.0. Magma fully supports CPF 1.1 and UPF 2.0, providing customers with a standard format for defining power intent for Talus Power Pro, Magma's low-power optimization technology. Talus Power Pro now supports donut-shaped voltage islands which are a technique for reducing power consumption by varying the voltage in the donut region. Talus Power Pro's industry-leading multiple voltage domain (MVdd) system and dynamic voltage and frequency scaling (DVFS) low-power technique provide customers with maximum performance per watt. These capabilities, combined with Magma's Hydra™ hierarchical design planner, allow customers to design very large, low-power systems on chips without sacrificing performance.
DFM Features for Variation-Aware Design Flow
To address manufacturability and variability issues at 28 nm, Magma fixes lithography hot spots directly in its Talus Vortex place-and-route tool. Utilizing TSMC's iLPC (Interoperable Lithography Process Check) format, markers indicate litho hot spots in the layout that are fixed within the Talus unified IC design environment, avoiding area and timing penalties while providing design-rule-clean layout. An important new capability in Reference Flow 11.0 is timing-driven pattern-based fill and dummy via insertion during routing. This is a requirement for physical designs at 40 nm and below and is provided by Talus qDRC in conjunction with Talus Vortex. Lastly, to manage stress effects, a new design-for-context feature has been added to the Talus Vortex placer that accounts for the effects of transistor layout within cells and their impact on timing. Talus Vortex places incompatible cells further apart during layout to improve manufacturability.
Magma Product Support for TSMC Reference Flow 11.0
Reference Flow 11.0 is supported by Magma's full RTL-to-GDSII suite of tools, which includes:
- Talus Design – physically aware RTL synthesis
- Talus Vortex – DFM-aware physical implementation
- Talus Power Pro – low-power optimization
- Hydra – hierarchical design planning
- Talus qDRC – timing-aware metal fill
- Quartz DRC – sign-off-quality design rule checking
- Tekton – sign-off-quality static timing analysis
More information on Magma's Talus, Hydra, Tekton and Quartz and the TSMC Reference Flow 11 will be available in Magma's booth 602 and the TSMC Open Innovation Forum booth 294 at the 47th Design Automation Conference (DAC) June 14-16 at the Anaheim Convention Center in Anaheim, Calif.