Cadence Design Systems, a company that delivers electronic design solutions, declared that Samsung Electronics has introduced the Cadence unified digital flow for producing a test chip at 20 nm.
The Cadence RTL-to-GDSII flow and methodology were combined to satisfy the needs of the latest 20-nm process technology from Samsung for the test chip. The flow managed IP validation and integration and complicated design regulations at 20 nm.
This innovation reveals the effectiveness of Samsung’s manufacturing and design techniques at advanced nodes and the ability of the Cadence digital flow to progress to the next advanced node. Moreover, this achievement demonstrates that important factors of the design chain such as libraries, IP, software, and foundry enablement meet crucial design regulations at 20 nm.
Samsung developed and implemented a project with an ARM Artisan Physical IP and ARM Cortex-M0 microprocessor using the Cadence 20-nm digital technique to develop a logic test chip that meets the design requirements at 20-nm. This latest partnership at 20 nm promotes the relationship between the two companies on previous advanced node flows and design for manufacturing and signoff for the low-power high-k metal gate (HKMG) process technology from Samsung.
Source: http://www.cadence.com/