By Cameron Chai
Cadence, a global innovator of electronic design products, and Samsung Foundry, the foundry business of Samsung Electronics, have collaborated to develop design-for-manufacturing (DFM) infrastructure for production of advanced chips.
The DFM infrastructure is designed to address electrical variability optimization and physical signoff for 32-, 28- and 20-nm chip designs. Both systematic and random yield issues are tackled allowing better designs based on Cadence Virtuoso custom/analog and Cadence Encounter digital implementation solutions.
The DFM technology has been integrated into advanced-node flow of Samsung Foundry to set up an infrastructure for SoC and ASIC designs. Traditional DFM advances the stage to digital and custom design for chips, which lead to lesser risk, and better profitability, predictability and productivity. The DFM flows at Samsung Foundry utilize many technologies from Cadence including, yield analyzer and optimizer, litho physical analyzer, pattern classification and search, and CMP predictor.
The new infrastructure has been optimized for advanced nodes, which allow Samsung Foundry to utilize hierarchical pattern matching and design approach for conducting accurate and effective systematic failure analysis. The Cadence Virtuoso custom/analog implementation and Cadence Encounter digital solutions allow production of first-time-correct silicon. The complexity in manufacturing is increasing at advanced nodes and this affects the time to yield and the design cycle times.
Customers of Samsung Foundry can utilize signoff pattern and in-design matching along with the automated fixing flows provided in the Cadence Encounter and Virtuoso solutions. The Cadence-Samsung Foundry collaboration has also yielded a chip-based CMP analysis flow for facilitating early meeting of topography yield issues in custom and digital designs.