Cadence Design Systems has unveiled an advanced Cadence Encounter RTL-to-GDSII flow for giga-scale, high-performance designs that include those at the newest 20 nm technology node.
The latest RTL-to-GDSII design, implementation and signoff flow is a result of Cadence Design Systems¡¯ close partnership with major foundry and IP partners and customers. It fulfills or surpasses the current market requirements on power, area and performance, allowing more efficient development of sophisticated low-power, high-performance SoCs.
The advanced digital flow is equipped with Cadence physical verification system, Cadence QRC extraction, Encounter power system, Encounter timing system, clock concurrent optimization, Encounter digital implementation system, Encounter eco designer, Encounter test, Encounter RTL compiler, and design for production technologies.
The new Encounter 20-nm approach offers silicon-proven 20-nm competencies with correct-by-construction double-patterning support, including capabilities from floor planning, position and routing to signoff physical, power and timing verification. This methodology allows highly effective engineering change order revisions and enhances 20-nm double-patterning designs¡¯ die area efficiency. Improved Cadence physical verification system offers foundry-qualified 20-nm in-design checking and final signoff verification to make sure DRC and double patterning color correctness.
The Encounter RTL-to-GDSII flow also features the latest GigaOpt engine, which physically optimizes the physical-aware synthesis technology, providing better correlated results and quicker timing closure. Moreover, the latest differentiated CCOpt technology physically optimizes clock tree synthesis, improving design performance by 10% and decreasing clock tree area and power by up to 30%. The latest release also features GigaFlex technology that widens the capacity to deal largest designs of ¡Ý100 million instances. Moreover, automated functional ECO technologies gear up pre- and post-mask ECO modifications, which are decreased to days or hours by means of smart hierarchical design handling.