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Synopsys Achieves Major Milestone in 28 nm Silicon Process Technology Node

Published on March 30, 2012 at 2:18 AM

By Cameron Chai

Synopsys declared that its parasitic extraction solution called StarRC has facilitated over 150 successful 28-nm tapeouts, providing the signoff accuracy and rapid turnaround time needed for next-generation of designs across applications such as mobile, consumer, computer and wireless communications.

StarRC's sophisticated modeling of complicated process occurs at the 28-nm silicon process technology node and its validation by major silicon foundries offers enhanced opportunity and reduced design risk for successful one-pass tapeout. Already, over 40 semiconductor companies are using this parasitic extraction solution for their 28-nm design signoff, corroborating its status as the gold standard extraction solution of the industry via numerous generations of process technologies.

Companies that have validated and chosen the StarRC parasitic extraction solution for their 28-nm tapeout flows and design signoffs comprise Toshiba, STMicroelectronics, Samsung, Renesas Electronics, Qualcomm, NVIDIA, Moortec Semiconductor, LSI, Imagination Technologies, HiSilicon Technologies, Fujitsu Semiconductor, Bull, Altera and much more.

The Senior Vice President and General Manager for Implementation Group at Synopsys, Antun Domic stated that offering an extraction solution that facilitates the company’s customers to confidently reach their signoff objectives is a top priority at every new process node. Surpassing the 150-tapeout landmark at 28-nm process node reinforces the StarRC’s capabilities and the company’s close partnership with foundries. It also confirms the capabilities of StarRC in promoting numerous customer designs.

Synopsys offers intellectual property, software, and services utilized in the design, production and verification of electronic systems and components.

Source: http://www.synopsys.com/

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