Jun 1 2013
Berkeley Design Automation, Inc., provider of the world’s fastest nanometer circuit verification, today announced that TSMC is using Analog FastSPICE Mega (AFS Mega™) for memory IP verification. Memory IP circuits implemented in 16-nm and smaller FinFET-based process nodes must meet stringent performance targets while requiring six-sigma bit cell yield to meet cost and power targets.
Analog FastSPICE Mega is the silicon-accurate circuit simulator that can handle up to 100M-element memories and other mega-scale arrays. Unlike digital fastSPICE tools that sacrifice accuracy via partitioning, event simulation, netlist simplification, table-lookup models, and other shortcuts, AFS Mega meets foundry required accuracy on 100M-element arrays. AFS Mega features unique capabilities to robustly, accurately, and quickly handle pre-layout and post-layout mega-scale arrays providing the silicon-accurate time, voltage, frequency, and power resolution and doing so faster than legacy digital fastSPICE tools.
“We are delighted that TSMC has adopted Analog FastSPICE Mega for FinFET-based memory IP Verification,” said Ravi Subramanian, president and CEO of Berkeley Design Automation. “As the industry leader in advanced process technology and embedded memory IP, TSMC’s choice affirms Berkeley Design Automation’s entry into the memory verification market with AFS Mega.”
The Analog FastSPICE (AFS) Platform provides the world’s leading circuit verification for nanometer-scale analog, RF, mixed-signal, mega-scale arrays, and custom digital circuits. The AFS Platform delivers nanometer SPICE accuracy and faster runtime performance than other simulators. For circuit characterization, the AFS Platform includes comprehensive silicon-accurate device noise analysis and delivers near-linear performance scaling with the number of cores. For large circuits, it delivers 100M-element capacity, the fastest near-SPICE-accurate simulation, and the fastest, most accurate mixed-signal simulation. Available licenses include AFS circuit simulation, AFS Nano, AFS Mega, AFS Transient Noise Analysis, AFS RF Analysis, AFS Co-Simulation, and AFS AMS.
“The move to the 16-nm FinFET process with multiple patterning and new transistors requires new approaches for accurate memory IP verification,” said Suk Lee, TSMC Senior Director, Design Infrastructure Marketing Division. “With BDA’s Analog FastSPICE Mega, we can accurately characterize post-layout FinFET-based memory arrays.”
Source: http://www.berkeley-da.com/