Cadence Announces IP Solutions for Third-party Designs Available on 28nm FD-SOI Process

Published on May 16, 2014 at 5:11 AM

Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced the immediate availability of two intellectual property (IP) solutions for third-party designs on the 28nm FD-SOI process node that is accessible via the recently announced agreement between STMicroelectronics and Samsung Electronics.

On this new process node, the Cadence® Denali™ DDR4 IP supports up to 2667Mbps performance, enabling developers requiring high-memory bandwidth for applications such as servers, network switches, and storage fabric to quickly take advantage of the DDR4 standard. In addition, the ultra-low-power Cadence USB High-Speed Inter-Chip (HSIC) PHY IP is also available on this process, and is an ideal solution for inter-chip USB applications.

The Cadence Denali DDR4 IP solution consists of a DDR PHY and controller that have been verified in silicon for interoperability. The solution supports high-performance systems, including several unique features such as per-bit de-skew capability and low-jitter phase-locked loops (PLLs). Additionally, its compatibility to DDR3 and DFI 3.1 standards ensures interoperability with other IP and allows for multiple memory types to be used within the same design.

The Cadence HSIC PHY IP is a complete mixed-signal transceiver macro-cell that implements the USB 2.0 HSIC layer for USB 2.0 high-speed device and host applications. The integrated solution made up of the Cadence HSIC PHY interface with the STMicroelectronics HSIC PHY I/O features extremely low power consumption and silicon area.

Cadence also announced the qualification of its digital implementation, signoff and custom/analog design tools for the 28nm FD-SOI process, including Cadence Encounter® Digital Implementation System, Interactive Physical Verification System, QRC Extraction Solution, Tempus™ Timing Signoff Solution, Spectre® Simulator, Virtuoso® Schematic Editor, Virtuoso Analog Design Environment, and Virtuoso Layout Suite.

“Companies looking to take advantage of the performance and power benefits of 28nm FD-SOI need to know that they also have the IP solutions and tools that are qualified for the process,” stated Martin Lund, Cadence’s senior vice president and general manager of the IP Group. “From early on, Cadence has worked with STMicroelectronics on FD-SOI technology and can assure our customers that they can quickly implement these IP solutions and sign off their designs.”

“FD-SOI technology delivers superior energy efficiency at the 28nm node and allows for a wider range of dynamic voltage and frequency scaling, leading to higher processing power per watt, lower thermal dissipation, and extended battery life for portable devices,” said Philippe Magarshack, executive vice president, Design Enablement and Services, STMicroelectronics. “Having just announced a leading foundry partner and now adding prominent IP and EDA suppliers like Cadence expands the growing ecosystem, for the benefit of our mutual customers and the entire electronics industry.”

For more information on the Cadence Denali DDR4 IP, visit www.cadence.com/news/ddr4ip.

Source: http://www.cadence.com

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