Dec 9 2008
Demonstrating its leadership in developing alternative transistor materials and processes for next-generation logic and memory technologies, SEMATECH engineers will present five technical papers at the 54th annual IEEE International Electron Devices Meeting (IEDM), the world's premier forum for the presentation of applied research in microelectronic, nanoelectronic and bioelectronic devices, on December 15-17, 2008 at the Hilton in San Francisco, CA.
The papers were selected from hundreds of submissions, and will release new details on cutting-edge research on high -k/metal gate (HKMG) devices, including new advances in reliability, performance and materials understanding for planar and non-planar CMOS technologies.
“Our presence at this year’s IEDM once again demonstrates SEMATECH’s R&D strengths, our ability to spearhead innovation, enhance fundamental understanding and our focus on cost-effective manufacturing solutions in a materials driven scaling era,” said Raj Jammy, SEMATECH’s vice president of materials and emerging technologies. “Throughout the week, the semiconductor device community will have the opportunity to hear our technology experts describe the work we’re doing for our members and the industry on new materials for transistor scaling.”
Additionally, SEMATECH will host an invitational pre-conference workshop entitled “III-V CMOS on Si: Technical and Manufacturing Needs” on December 14. The workshop will focus on technical and manufacturing challenges affecting the use of III-V materials in CMOS devices. Co-sponsored by Aixtron AG, the workshop will include experts from Industry and Academia debating on the challenges and opportunities of III-V leading to an early understanding of key issues in the large-scale manufacturing use of elements in columns III, IV and V of the periodic table.