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Olympus P+R and Calibre Verification Platforms Qualified for 32nm IC Designs at STMicroelectronics

Published on March 2, 2009 at 6:02 PM

Mentor Graphics Corporation (NASDAQ: MENT) today announced that STMicroelectronics (NYSE: STM), a global leader in developing and delivering semiconductor solutions across the spectrum of microelectronics applications, has qualified the Mentor design-to-silicon platform for the physical implementation and verification of advanced IC products targeting the 32nm process node. The 32nm design flow includes the Olympus™-SoC multi-corner multi-mode place-and-route system, the sign-off standard Calibre® verification platform with comprehensive DFM solutions addressing manufacturing variability, and the Eldo® SPICE simulator for library cell characterization.

“STMicroelectronics has selected Mentor’s design-to-silicon platform for its advanced capabilities that specifically target the challenges of 32nm and have a direct impact on our business. These challenges include the enormous complexity of new designs, the need for concurrent timing and power closure to reduce time-to-tapeout, and the ability to make designs resilient to variations in manufacturing,” said Philippe Magarshack, STMicroelectronics Technology R&D Group Vice President and Central CAD and Design Solutions General Manager. “Based on our experience with complex SoC implementations at 65/55nm and 45nm, the large capacity of Olympus allows us to handle large designs in flat mode, and to close many modes and corners simultaneously. At 32nm, Olympus’ close integration with Calibre for verification will allow us to quickly close the ‘DFM-integrity loop’ on large designs.”

“We are very pleased with the results of our long-term partnership with STMicroelectronics, which has led to their decision to adopt the Mentor implementation and verification tools for 32nm,” said Joseph Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics. “We have worked together to define the requirements and solutions for rapid design and verification of high-performance, low power 32nm ICs that ramp to volume production quickly and without surprises. The traction our implementation and verification solution is enjoying in the marketplace is a good indication that we have addressed customers’ most pressing concerns.”

Mentor’s Design Flow for 32nm

The Olympus-SoC implementation platform was architected from the ground up to address the key challenges of physical design at 32nm. It provides native concurrent multi-corner multi-mode optimization, DFM-aware routing, automation for all low power design methodologies, 100M+ gate capacity, full multithreading, and the industry’s only parallel timing engine to deliver efficient scaling on multicore, multiprocessor computing platforms.

The Calibre nm platform, with the Calibre nmDRC and Calibre LVS tools, has become the golden standard for verification of advanced ICs. Mentor’s comprehensive DFM solution is tightly integrated with the Calibre platform and supports the highest performance designs at 32nm with better control of manufacturing variability for cell libraries as well as full-chip layouts. The Calibre DFM solution includes the Calibre LFD™ product, which provides accurate modeling of lithographic process and etch characteristics, and is the standard sign-off flow for litho hotspot and variability analysis for IP and full-chip applications. It is fully integrated with the Calibre nmDRC, Calibre LVS (Layout vs. Schematic) and Calibre xRC™ products, allowing critical device and interconnect characteristics to be extracted based on accurately modeled, “as-built” contour geometries. The resulting physical data can be plugged into Mentor’s Eldo high-performance SPICE simulator, the first tool available for the STMicroelectronics 32nm cell library characterization flow, to produce an accurate timing simulation of how physical blocks will actually perform.

The Calibre DFM solution also includes the Calibre YieldAnalyzer and Calibre YieldEnhancer products for automated CAA analysis and fixing. The YieldEnhancer tool includes a SmartFill intelligent fill capability, which performs metal fills based on metal density and density gradients. The Calibre CMPAnalyzer tool enables CMP planarity analysis and fill enhancement based on comprehensive, foundry-specific thickness models. Together, these products comprehensively address the variability issues of manufacturing at 32nm by making the physical design flow more process-aware and robust, reducing yield surprises late in the development cycle.

Posted March 2nd, 2009

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