Magma(r) Design Automation
Inc. (Nasdaq:LAVA), a provider of chip design software, today announced
that the Talus(r) IC implementation system has been included in TSMC Reference
Flow 10.0. With Magma software and the latest TSMC Reference Flow, designers
have access to the "Fastest Path to Silicon(tm)" for designs targeted
at TSMC's 28-nanometer (nm) processes.
"TSMC 28-nm processes offer the promise of billion-gate ICs, but also
bring the challenge of dealing with more physical effects, tougher power requirements
and difficult timing closure issues," said Premal Buch, general manager
of Magma's Design Implementation Business Unit. "Magma's latest release,
Talus 1.1 with our new COre(tm) technology, combined with TSMC's Reference Flow
10.0, provides faster design closure on large, tough designs."
COre is Magma's new Concurrent Optimizing routing engine. This new routing
engine, which includes the ability to push critical wires to a thicker and wider
metal layer, supports TSMC's 28-nm design rules and provides faster overall
design closure with better performance and predictability.
"For years TSMC has been leveraging close collaboration with leading EDA
vendors, such as Magma, to co-optimize EDA design technology and our advanced
process technology," said S.T. Juang, senior director of Design Infrastructure
Marketing at TSMC. "With the inclusion of the Talus system for Reference
Flow 10.0, TSMC and Magma offer mutual customers differentiated design and process
technologies that improve power, performance and design for manufacturability
of 28-nm ICs."
Enabling 28-nm Design through the Open Innovation Platform (OIP)
Through the OIP and Active Accuracy Assurance initiative, TSMC enables innovation
by promoting quality and accuracy throughout the semiconductor ecosystem. Magma
software has supported the OIP since the platform's inception. Magma works closely
with TSMC and mutual customers early in the R&amp;amp;amp;amp;D
process to ensure product enhancements satisfy customers' deployment requirements.
By engaging with TSMC and customers early, Magma has ensured that Talus is able
to implement designs targeted at TSMC's 28-nm processes.
Enhanced Low-Power Design Techniques
Low-power support in Reference Flow 10.0 has been expanded to include the bottom-up
hierarchical Unified Power Format (UPF) flow. The UPF can be used to specify
low-power design techniques at all levels of a hierarchical design flow. For
low-power flows with multiple voltage islands, support for disjoint power domains
with dual power SRAMs is now available. To address leakage, Talus is able to
optimize leakage at different corners from timing optimization. This provides
more accurate timing and leakage optimization, minimizing iterations. Talus
also supports the Common Power Format (CPF) as part of its low-power flow.
Ensuring Manufacturability at 28 nm
To address design for manufacturability (DFM) and variability issues at 28
nm, Magma integrates Talus qDRC physical verification capabilities into the
Talus Vortex place-and-route flow. This solution provides highly accurate timing-driven
metal fill that is design-rule clean and meets timing and performance requirements.
Other physical DFM capabilities include lithography hotspot fixing within Talus
based on TSMC qualified lithography process check (LPC) hotspot detection engines.
By fixing hotspots within the Talus unified design environment, area and timing
penalties can be avoided and a design-rule-clean layout is generated. For electrical
DFM, TSMC provides an integrated eDFM (electrical DFM) analysis, which is a
combination of DFM effects on chemical mechanical polishing (CMP), Thickness-to-Electrical
(T2E), lithographic Shape-to-Electrical (S2E), and stress effects. Talus provides
complete support for TSMC's eDFM-based timing analysis and optimization.