STMicroelectronics (NYSE:STM) , a world leader in system-on-chip technology, today introduced the industry's first embedded microprocessor that couples two ARM Cortex-A9 cores with a DDR3 (Third-generation double-data rate) memory interface.
Manufactured in ST's low-power 55nm HCMOS (high-speed CMOS) process technology, the SPEAr1310 delivers high computing power and customizability for multiple embedded applications together with the high level of cost competitiveness offered by system-on-chip devices.
The new microprocessor combines the unrivalled low power and multi-processing capabilities of the ARM Cortex-A9 processor core with innovative Network-on-Chip (NoC) technology. The dual ARM Cortex-A9 processors support both fully symmetric and asymmetric operations, at speeds of 600MHz/core (industrial worst-case conditions) for 3000 DMIPS equivalent. NoC is a flexible communications architecture that enables multiple different traffic profiles while maximizing data throughput in the most performance- and power-efficient way.
"SPEAr1310 is the first device in the recently announced SPEAr1300 family and others will follow shortly," said Loris Valenti, General Manager of STMicroelectronics' Computer Systems Division. "With its innovative architecture and powerful feature set, SPEAr1310 is at the leading edge of the embedded processor market and enables an unprecedented mix of cost competitiveness, performance and flexibility."
Equipped with an integrated DDR2/DDR3 memory controller and a full set of connectivity peripherals, including, USB, SATA and PCIe (with integrated PHY), in addition to a Giga Ethernet MAC, ST's SPEAr1310 microprocessor targets high-performance embedded-control applications across market segments from communication and computer peripherals to industrial automation.
Cache memory coherency with hardware accelerators and I/O blocks increases throughput and simplifies software development. The Accelerator Coherency Port (ACP), coupled with the device's NoC routing capabilities, addresses the latest application requirements for hardware acceleration and I/O performance. ECC (Error Correction Coding) protection against soft and hard errors on both DRAM and L2 Cache memories dramatically improves the Mean-Time-Between-Failures for enhanced reliability.