Cadence Design Systems, Inc. (NASDAQ: CDNS), a leader in global electronic design innovation, today announced that IMS CHIPS has adopted Cadence® Silicon Realization technologies for its special mixed-signal gate array technology.
IMS CHIPS plans to deploy Cadence end-to-end Virtuoso® custom and Encounter® digital technologies for its commercial research business in areas such as advanced silicon technology, customer-specific circuits, nanopatterning and image sensor technology.
IMS CHIPS supports small- and medium-sized companies in Germany with the development, manufacturing and application of microelectronic systems. At the same time, the Stuttgart-based institute is a respected research partner for innovative technologies and collaborates with international leading semiconductor companies and suppliers. An important consideration for IMS CHIPS was to establish and build an industry-leading, end-to-end design flow from a single source that would provide compatibility with its customers and foundries and could offer a comprehensive approach from initial design development to simulation, all the way to tape-out. Another important factor in the decision to standardize on Cadence Silicon Realization technologies was the ability to address complex routing requirements using only two layers of interconnects -- a challenge that most existing and new routers on the market are not able to handle.
"We teamed with Cadence because there is no comparable product on the market that offered us a similar solution to tackle our complex mixed-signal gate array technologies," said Professor Dr. Joachim Burghartz, director and chairman of the board of directors at IMS CHIPS. "Another important criterion to us was to use a proven solution with a long track record of silicon success, to help us avoid risk and time-consuming iterations. The excellent local support we received from Cadence's channel partner, FlowCAD, was a strong factor in our decision as well."
The Cadence approach to mixed-signal design leverages an integrated mixed-signal methodology in which early design planning, front-end design, functional verification, physical implementation, and packaging are shared responsibilities between analog and digital teams. This is the driving force and unique advantage of Cadence Silicon Realization -- providing a more deterministic path to silicon by driving pervasive design intent, abstraction, and convergence across the entire flow. IMS CHIPS will benefit from the interoperability between the Virtuoso and Encounter technologies, helping them to accelerate their development time. For IMS CHIPS with its focus on small- and medium-sized companies, this is critical to more effective business planning.
"Advanced customers such as IMS CHIPS need an end-to-end design flow that is mature and capable of handling complex requirements for complex chip design," said David Desharnais, group director of product marketing at Cadence. With Cadence Silicon Realization's proven mixed-signal flow, IMS CHIPS was able to replace their previous commercial point tools with a complete solution that perfectly addressed their needs.