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Cascade Microtech and imec Collaborate to Test New 3D-TSV Integrated Circuit

Published on March 4, 2011 at 4:26 AM

Cascade Microtech, Inc. (NASDAQ: CSCD), a leading expert at enabling precision measurements of integrated circuits at the wafer level, and the nanoelectronics research center imec, today announced they have entered into a collaborative research partnership for testing and characterization of 3D integrated circuit (IC) test structures.

Imec will work closely with Cascade Microtech to develop test methods and methodologies for emerging 3D Through-Silicon-Via (TSV) structures, and to lead the way in development of global standards for 3D IC development and production test.

Demand for tablet PCs and smartphones is driving processor vendors to utilize 3D-TSV techniques to stack memory on processors, achieving higher performance without the need for node shrinks. 3D-TSV stacked ICs, still an emerging technology, allow multiple chips to be stacked and integrated into a single package, reducing the form factor, reducing power consumption and increasing the bandwidth of inter-chip communication by eliminating connections through the circuit board. Chip stacking with 3D-TSV interconnects requires Known-Good-Die (KGD) wafer probing with high test coverage before stacking in order to achieve practical stack yields. The high density of TSV interconnects has challenged conventional probe card architectures thus limiting electrical test access.

The complexities of test inherent in new 3D-TSV integrated circuit designs will be a key focus of the research project that will take place at imec's research facilities in Belgium, where silicon wafers with test probe structures of 40 micron pitch and smaller will be manufactured and tested. In the process of ongoing research, imec will install the first turnkey 3D test solution comprising of a 3D-TSV probe station and a new probe card from Cascade Microtech. The probe station and probe cards will be used to characterize the through-silicon-vias in the chip stacks as part of ongoing efforts to optimize 3D stacked integrated circuit performance and reliability.

"The complexity of the 3D-system supply chain is reflected in the partner portfolio of imec's 3D research program where leading IDMs, foundries, fabless companies, OSATs, equipment and material suppliers as well as EDA companies partner to develop and improve 3D technologies. A good alignment of these multi-disciplinary forces is required to make 3D-system integration an industrial reality," said Erik Jan Marinissen, imec Principal Scientist. "The collaboration with Cascade Microtech in this early phase of engineering and development will enable us to identify challenges and provide solutions for test issues that are specific for 3D integrated systems. Enabling probing solutions for high-density interfaces, minimizing the impact of pre-bond testing on stacking yield and test access to buried layers are key challenges for testing 3D systems that we will address through this collaboration.

"Ongoing research is critical for Cascade Microtech's 3D-TSV solution path, and imec is a key collaboration partner for our development efforts, given its history of successful research collaboration, its superior research facilities, its commitment to the semiconductor industry and the expertise of its staff," said Michael Burger, President and CEO, Cascade Microtech, Inc. "In recent years, probing and test were viewed as a major barrier to 3D-TSV development and manufacturing. We are looking forward to breaking through the barrier, paving the way for our mutual customers to quickly achieve extremely cost-effective 3D-TSV test solutions."

Source: http://www.cmicro.com/

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