By Cameron Chai
SEMATECH experts highlighted new developments in wafer bonding at the 7th Annual Device Packaging Conference (DPC) held between March 7 and 10 in Scottsdale, Arizona. This will enable cost- effective and precise packaging of three dimensional technology.
Technologists showed a die-to-wafer interconnect process with a die-tacking and collective-bonding method on a 300mm wafer platform for three dimensional IC applications. Composite wafers comprising a 50µm thin through-silicon-via (TSV) wafer bound to a supporting handle wafer were treated with dice using a short, low-temperature tacking process. This caused rapid die-to-wafer integration that is required for heterogeneous three dimensional IC.
Wafer-to-wafer (WtW) bonding is a primary requirement for three-dimensional wafer interconnection via stacking. The International Technology Roadmap for Semiconductors (ITRS) guide to high density, intermediate level, TSVs specifies via diameters of 0.8 to 4.0µm in 2012 and beyond. Three dimensional ICs will impact the semiconductor industry, due to their capacity to overcome scaling limitations, enhance performance and capability in a cost- effective manner.