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Posted in | Nanoelectronics

Cadence EDI Used by Freescale Semiconductor to Tapeout 28nm QorIQ T4240 SoC

Published on August 17, 2013 at 8:29 AM

Cadence Design Systems, Inc., a leader in global electronic design innovation, today announced that Freescale® Semiconductor used the latest release of Encounter® Digital Implementation (EDI) System to tapeout its next generation QorIQ® T4240 system on chip (SoC) running at 1.8 GHz. The T4240 is based on multiple 64-bit Power Architecture® clusters of high-performance e6500 processors and modern system peripherals.

Freescale’s QorIQ processing platforms are complete SoCs for networking applications across carrier, enterprise cloud computing, military, and industrial markets. The highly integrated T4240 SoC has a complex floorplan with multiple hierarchical blocks, 12 Power Architecture 64-bit processors, high-speed I/O, on-chip networking, high-speed cache coherency interconnect fabric, and complex clocking schemes, requiring high performance and power efficiency.

“Our T4240 SoC represents a great step forward in our high-performance QorIQ T series product line targeted for demanding networking applications. Cadence’s GigaOpt technology helped us achieve aggressive time to market for our next generation T4240 SoC,” said Ken Hansen, vice president and chief technology officer, Freescale Semiconductor. “We were also able to realize better design performance, smaller silicon area, and improve design team productivity.”

GigaOpt is a new multi-threaded physical optimization technology included as standard in the latest EDI System release for pre-route, post-clock tree synthesis, and post-route optimization. GigaOpt also includes new layer-aware timing-driven net buffering and critical path replacement algorithms which deliver significant improvements in design performance, area, and power.

“We are committed to developing innovative technologies that address the most demanding design challenges facing the industry,” said Dr. Chi-Ping Hsu, chief strategy officer, EDA, and senior vice president, Digital and Signoff Group at Cadence. “Freescale has been a great partner to Cadence and we are pleased to see GigaOpt bring such significant performance and schedule improvements to Freescale’s state-of-the-art SoC designs.”

Source: http://www.cadence.com/

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