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Soitec's 300mm Ultra-Thin SOI Wafer Platform Ready to Support FD Device Applications

Published on June 15, 2009 at 9:01 PM

The Soitec Group (Euronext Paris), world's leading innovator and provider of the engineered substrate solutions that serve as the foundation for today's most advanced microelectronic products, announced today that its 300mm ultra-thin SOI (UTSOI) wafer platform is qualified and ready to support fully depleted (FD) device applications scheduled on the industry's CMOS roadmaps for 22nm and beyond. Soitec introduced its 300mm UTSOI wafer platform, fabricated using the company's patented Smart Cut™ technology, at SEMICON West last year, and since then has been actively working on product options, process optimization, and internal and customer qualifications.

The latest breakthrough is Soitec's ability to manufacture SOI with extremely thin top-layer silicon (20nm) to a thickness uniformity tolerance of ±5 Å (angstroms) in high volume with high yields. The specific parameters of the final SOI substrate can be tailored to customer applications, and manufactured with the same yields and similar costs as the current generation of mainstream SOI wafers.

FD SOI has been used commercially for many years, but mainly for niche applications. Now industry leaders are reporting the advantages of fully depleted SOI for mainstream applications. “On fully depleted SOI, we've demonstrated 25nm high-k metal-gate devices with matching characteristics far superior to those obtained on bulk silicon,” reported Dr. Olivier Faynot, Director of Advanced SOI technologies Development at CEA-Leti. “As it eliminates the need to dope the channel region, FD SOI solves threshold voltage (Vt) variability challenges at current and future nodes, while maintaining excellent Ion and Ioff characteristics and drastically reducing gate leakage current. With this uniform ultra-thin film SOI substrate, Soitec is delivering a solution for substantially improving Vt control of the CMOS device.”

“UTSOI provides a solid foundation for planar and ultra-thin body devices, giving designers the ability to drastically cut power consumption and leakage while preserving performance. It simplifies the overall CMOS architecture, thus reducing the cost of ownership below a bulk approach,” stated Paul Boudre, Chief Operating Officer of the Soitec Group. “We are fully prepared to support our partners in fine tuning their manufacturing process steps to meet ultra uniformity requirements, and deliver maximum value from this ultra-thin layer advantage.”

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