Silicon Frontline
Technology, Inc. (SFT) announced today that its 3D extraction software for
post-layout verification, F3D (Fast 3D), has been validated by semiconductor
foundry United Microelectronics Corporation (NYSE: UMC) (TSE: 2303) ("UMC"),
a leading global semiconductor foundry, for UMC's 40 and 65nm processes. F3D
provides field solver accuracy for full-chip design, enabling higher quality
extraction and faster post-layout verification closure.
UMC qualified Silicon Frontline's F3D for post-layout verification because
it guarantees accuracy and high performance by using rigorous 3D technology
to extract parasitics. Users can specify the level of accuracy desired, net
by net, at the block level or with regular expressions. By guaranteeing accuracy,
Silicon Frontline is ensuring the resulting parasitics are correct within the
user-specified accuracy.
"Qualifying design tools such as Silicon Frontline's F3D aids our customers
in choosing the software they need to design complex, high performance ICs and
to confidently achieve silicon success," said Stephen Fu, IP Development
and Design Support director, at UMC. "The combination of F3D technology
with our advanced manufacturing processes, gives customers a more predictable
and smoother flow to silicon success."
"We are pleased to have one of the world's leading foundries, UMC, support
our 3D extraction software for post-layout verification of designs targeting
its advanced processes," said Yuri Feinberg, CEO. "With our software,
UMC customers can experience Guaranteed Accuracy with full-chip capacity and
performance."
Silicon Frontline announced the company and its first EDA software products
in May. F3D is ideally suited for sensitive analog and AMS circuits where coupling
is a challenge -- ADCs, DACs, circuits with differential signals, MIM/MOMCaps
and 3D devices, image sensors, RF and high speed designs and for circuits manufactured
at advanced technology nodes, such as 65 and 45nm.