Feb 16 2010
Specialized sensors to measure the amount of mechanical stress caused by the process to thin semiconductor wafers-used to pack ever-increasing amounts of processing power into ever-decreasing spaces-have been designed, fabricated and calibrated by an international research team involving A*STAR researchers.
“The demand for miniaturization and the integration of many functions into a single product has led to the development of chip-stacking technology,” says team member Xiaowu Zhang from the A*STAR Institute of Microelectronics. However, fabrication technology has advanced to the point where the density of devices on the surface of a semiconductor wafer is approaching the limits imposed by physics. Reducing the substrate thickness allows for further space savings, but the thinning induces a residual stress in the wafers that makes them susceptible to damage.
Zhang and his co-workers in collaboration with scientists from the Georgia Institute of Technology, USA, and Infineon Technologies, Germany, therefore studied the stresses that silicon substrates must endure because of the thinning process1. First, the team needed to develop in situ sensors. As luck would have it, silicon has very strong piezoresistive properties; that is, an applied force changes its electrical resistance.
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