Jun 22 2010
Hiroyuki Akinaga, the Nanodevice Innovation Research Center of the National Institute of Advanced Industrial Science and Technology, and Hisashi Shima, Superior Nano-interface Device Research Team of the center, have developed a process for integrating low-power, high-speed, and non-volatile resistance random access memory (RRAM) devices on a 128-kbit memory chip and have succeeded in fabricating chip arrays on an 8-inch wafer.
This research has been performed in collaboration with Sharp Corporation, the Institute of Semiconductor & Electronics Technologies of ULVAC, Inc., and Akio Kitagawa and Kazuya Nakayama of the Graduate School of Natural Science and Technology, Kanazawa University.
This RRAM chip array was fabricated by using the existing semiconductor manufacturing process and uses neither expensive components such as noble metal electrodes nor materials requiring special handling. Because of this, it is a memory device that is bit-cost competitive and saves natural resources and energy.
RRAM is the key to energy efficiency in the areas of information and electronics, in which the use of devices with the ability to handle large amounts of information at high speed is becoming increasingly important. Our research has led to the development of a platform for evaluating the performance and reliability of RRAM devices at the chip and wafer levels. Our next goal is the early application and commercialization of this new memory device.
This achievement will be presented on May 18 at the 2nd International Memory Workshop in Seoul, Korea, from May 16 to 19, 2010.