Silicon Frontline Technology (SFT) has proclaimed that it is planning to introduce the first commercial hierarchical 3D extractor, H3D to be used for post-layout verification. H3D would give hierarchical netlisting, hierarchical parasitic extraction, field solver accuracy and unlimited capacity by working along with design flows from prominent EDA suppliers.
Yuri Feinberg, who is the CEO of SFT, has revealed that post layout verification was a major block in the present day leading edge designs and that the introduction of H3D would remove the bottleneck by offering a precise extractor which operates with sub-linear performance and also gives a hierarchical output for post-layout simulation speed up.
H3D is perfect for repetitive design and array-based structures such as FPGAs, memories and image sensors. Its performance is sub-linear which guarantees that the extraction performance improves along with the growth of the design size. The results are dependent on the design but have revealed improvements in performance from 20 to 120 times in comparison to flat extraction. Users could specify the accuracy needed on a block by block or net by net basis and H3D also offers unlimited capacity mainly because of the parallelization and hierarchical extraction. The hierarchical output supports C, R, RCCc and distributed RC. It would be ready for shipping by the third quarter.
Source: http://www.siliconfrontline.com