Mentor Graphics, in partnership with STMicroelectronics has successfully taped out a 20 nm test chip, representing a key landmark in the advancement of a full Mentor design-to-silicon solution for future-generation production technology.
The place and route system called Olympus-SoC used for the implementation of the test chip was validated using the Calibre nmDRC platform, which is used by R&D teams at STMicroelectronics for verification and double patterning. The combination of the Tessent, Calibre and Olympus-SoC silicon test and output analysis products offer a complete flow for the development of 20 nm integrated circuits.
The Olympus-SoC, a comprehensive netlist-to-GDSII solution, is developed on an increased capacity data model, patented synchronized multi-corner multi-mode optimization, sophisticated low-power functionalities and incorporation with the Calibre system for rapid production closure. Its OpenRouter architecture supports Calibre engines in design process and utilizes the foundry signoff decks to make the layout DFM, LVS and DRC signoff clean and decomposable for multi-patterning.
The General Manager of the Route Group and Mentor Place, Pravin Madhani stated that partnering with STMicroelectronics as an expert and strategic investment collaborator in the DeCADE program has allowed the company to deliver sophisticated implementation solutions at the 20 nm process node.
STMicroelectronics Technology Research and Development’s Group Vice President, Philippe Magarshack stated that ultra-low power, larger design sizes, lithography restrictions and augmented process variability and intricacy are the design challenges of integrated circuits at the 20 nm node. The company closely works with Mentor Graphics on many features of 20 nm design enablement via the DeCADE and the ISDA joint development program, he said.
Source: http://www.mentor.com/