By Cameron Chai
Synopsys has declared that its physical verification product, IC Validator has been certified by GLOBALFOUNDRIES for 65, 40 and 28 nm physical signoff, with immediate accessibility to layout-versus-schematic and design rule check runsets to customers of GLOBALFOUNDRIES.
IC Validator, a component of the Galaxy Implementation Platform, is a suitable component for IC Complier for performing In-Design Physical Verification, enabling place and route engineers to reduce tapeout cycle time by avoiding manual repairs and late-stage issues. The certification allows designers working on the 65, 40 and 28 nm process technology nodes of GLOBALFOUNDRIES to use the special advantages of In-Design Physical Verification.
With its command-processing engine and expandable hybrid data, IC Validator will offer a strong platform for coding and assessing the difficult edge- and polygon-based rules needed for up-and-coming process nodes. It automates processing of tedious lower-level data and allows coding at higher abstraction levels. Its near-linear scalable architecture optimizes mainstream hardware use through the utilization of memory-aware, intelligent, load balancing and scheduling technologies. These features help GLOBALFOUNDRIES to update the development and application of design rules and provide superior scalability and accuracy to common customers involved in sophisticated process nodes.
In-Design Physical Verification is a brilliant combination of IC Compiler and IC Validator that allows place and route engineers to carry out automatic signoff-quality analysis prior to the finalization of the design while automating corrections. In-Design technology provides high-production capability such as quick ECO validation, timing-aware metal fill and automatic DRC repair, all inside the place and route setup. In-Design Physical Verification eliminates high-cost iterations of downstream analysis tools and maintains convergent design advancement to physical signoff.