By Gary Thomas
Directed Self Assembly technique that was previously used only in laboratories for test circuit structures has been successfully extended to real circuits of 22 nm by researchers at the Stanford University.
The research, which is funded by the Semiconductor Research Corporation (SRC) offers an environment friendly and economical option to fabricate smaller circuits down to the range of 14 nm as opposed to current lithography techniques, which make it difficult to accurately create contact holes that connect the substrate and semiconductors.
The new technique involves use of a block copolymer film to coat the surface of the semiconductor wafer. Conventional lithography methods are employed to create irregular indentations on the wafer surface which serve as a template for directing the block copolymer molecules into self-assembled arrangements. The contact holes can be spaced closely by changing the size of the indentations. Such closely packed patterns facilitate the building of very small chips. The new technique scores high on environmental safety as the researchers have used polyethylene glycol monomethyl ether acetate (PGMEA) as the solvent in the coating and etching process. The cost savings are also high compared to lithography tools that cost huge amounts per tool.
A host of companies ranging from chip manufacturers to fabrication-less design companies stand to gain from this research. The technique can be extended to other nano level applications outside the area of electronics. The researchers are now in the process of developing tools in consultation with automated electronic design experts to aid chip designers to specify the location of contact holes.