Cadence Design Systems has reported that the Cadence Physical Verification System (PVS) has been qualified by TSMC for 28-nm design signoff. In addition, TSMC has also concluded Phase I certification of Cadence PVS for its 20-nm process.
TSMC can now directly deliver a PVS 20-nm technology file to designers upon request to perform early design exploration. Moreover, TSMC-Online is now accessible to designers for downloading 28-nm technology files for signoff.
Cadence PVS is compatible with 20-nm technology in which advanced patterning technology is utilized. The dedicated PVS engine augments color loop detection accuracy, lowers false errors, and offers perceptual error reporting. Mask decomposition feasibility is also ensured by the Cadence technology.
The combination of Cadence PVS and Cadence Encounter digital and Virtuoso custom implementation platforms helps designers to identify and rectify errors early during the implementation stage. The integration of Cadence PVS with Virtuoso comprises in-design design rule checking (DRC) verification in real time; incremental DRC rectification and verification; and 20-nm DPT color loop detection in real time.
Silicon Realization Group’s Senior Vice President of Research and Development, Chi-Ping Hsu stated that the company and TSMC worked closely to provide innovative signoff and implementation technologies to design teams for SoC design and production. TSMC’s Phase I certification for its 20-nm process and its qualification of Cadence PVS for 28-nm design signoff are helpful in delivering convergent verification capabilities for intricate mixed-signal SoCs.
Suk Lee, Senior Director for Design Infrastructure Marketing Division at TSMC, stated that the two companies worked closely to get these results.
Source: http://www.cadence.com