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Posted in | Nanoelectronics

Avago Employs Cadence EDI to Boost Productivity on Large-Scale 28-nm Chip

Published on January 24, 2013 at 3:06 AM

Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today that Avago Technologies®, a leading supplier of analog interface components, used Cadence® Encounter® Digital Implementation (EDI) System to accelerate the design schedule and boost engineering productivity on a large-scale 28-nanometer networking chip.

Avago achieved performance of 1GHz, a 57 percent improvement compared to the previous software. In addition, full-chip implementation turnaround time improved through faster timing closure and fewer design iterations. Cadence is currently collaborating with Avago on its next high-speed networking chip -- a 150 million-gate design.

"By working with Cadence, we have boosted productivity for our 28-nanometer designs," said Frank Ostojic, vice president and general manager, ASIC Products Division at Avago. "The EDI System's new GigaOpt technology enabled improved runtimes, which is critical to hit the market windows for our large designs."

The EDI System provides an effective methodology to optimize power, performance, and area for high-performance, giga-scale designs. In addition, integrated "in-design" signoff capabilities in EDI System ensure correlation between timing and power calculations used during implementation and the final calculations produced by signoff engines, reducing iterations between the implementation and signoff stages, resulting in improved productivity for the design team.

GigaOpt technology -- introduced earlier this year in EDI System -- is a unique technology that integrates physical-aware synthesis technology with physical optimization, enabling faster timing closure and better correlated results. It is a highly scalable optimization technology that leverages multi-threaded processing in leading high-performance processors. In Avago's latest 28-nanometer design, GigaOpt's "route-driven" optimization, in which the tool takes into account routing layer considerations earlier in the flow, contributed significantly to the improved quality of results obtained during timing optimization.

"Avago was faced with the challenge of moving a remarkably complex design to market quickly while maintaining the ambitious metrics that ensure high-quality silicon," said Dr. Chi-Ping Hsu, senior vice president, Research and Development, Silicon Realization Group at Cadence. "The EDI System, with features like the GigaOpt engine, helped Avago meet its power, performance and area requirements for this large-scale project."

Source: http://www.cadence.com/

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