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3D-TSV Wafers Account for More Than 6% of Total Semiconductor Industry by 2015

Published on July 30, 2008 at 10:57 AM

Research and Markets has announced the addition of the "3-D TSV Interconnects - Equipment + Materials 2008 Report" report to their offering.

The Next Revolution for Semiconductor Packaging & Circuit Assembly Industries

The Semiconductor manufacturing industry is today facing more than ever the challenge to explore the so-called “More-than-Moore” 3-D integration route in order to pursue the continued aggressive scaling of the historical Moore’s Law. The whole Semiconductor industry supply chain is being concerned: from IDMs to Fabless and CMOS foundries, from OSATs to Substrate and Circuit Assembly players as well. We believe 3D integration with TSVs could accelerate even more current consolidation happening in CMOS wafer fabs and the shift toward a fabless foundry model. As the whole industry supply chain is being concerned, all players are at the moment positioning on the technology and evaluating about which 3-D technology platforms need to be invested and developed for their own business.

Times are bright for packagers from all across the world. A whole new infrastructure needs to be developed in the "Mid-end" of the semiconductor industry supply chain. New Technologies, Equipments and Advanced Materials coming both from the Front-end and the Back-end worlds are being developed and will give rise to a new revival of the semiconductor packaging and circuit assembly industries. Our latest market forecasts show that 3D-TSV wafers will be shipped in millions and have the potential to impact as much as 25% of the memory business by 2015. If we exclude memories, our analysis show that 3D-TSV wafers could account for more than 6% of the total semiconductor industry by 2015.

This new study aims at giving a better understanding about the right timeline for the successful adoption of the Through Silicon Via (3-D TSV interconnect) technology across the wide range of its driving end-applications. The two reports further quantify the potential impact of 3-D technologies on the semiconductor manufacturing market (at the Device / Equipment / Material levels) and evaluate how the industry supply chain is likely to evolve in the 2009-2015 time frames.

Examples of major finding from this new market research study are:

- Motivations for going to 3-D are pretty clear and have not changed much since the technology has been successfully introduced into production for MEMS and CMOS image sensors already: it is all about achieving smaller form factor with increased package densities, to meet bandwidth, RF, power consumption performance improvements and to keep with further cost reduction. Cost is definitively set to be the strongest motivation to develop 3D technologies in the long run. Additionally, we do see several players being driven by reliability motivations: higher reliability systems can be manufactured through the vertical integration of several layers using 3-D TSVs instead of wire-bonds or Flip-chip interconnects, using 3D stacked wafer level optics instead of plastic injection molded lens modules. From many point of views, 3-D appears to be a strong enabling driver for the successful introduction of ever more integrated new systems into harsh and space constraint application environments such as in the Automotive, Bio, Telecom and Consumer markets among others.

- Roadmap per application: WL-CSP CMOS image sensors are on the point to leave their traditional edge interconnects configuration for going to "real" 3D-TSV architectures as soon as this year. Vias will be partially or completely filled, depending on via filling approach being developed (Copper for partial filling, Poly-Silicon or Tungsten for completely filled vias). Additionally, we clearly see the number of I/Os expanding to several hundreds of interconnects per chip with a trend to stack the DSP chips under the image sensor chip itself. MEMS will also take benefit from 3-D in order to combine the MEMS with its ASIC while Wireless SiPs will combine heterogeneous layers all together (built on different lithography nodes, different material substrates such as Si, GaAs, SiGe...). The market for 3-D stacked memories is imminent: it is primarily driven by RAM based memories first meanwhile more and more Flash memory is set to be combined in the future within MCP, PoP/SiP packages, cell-phone card-slots and SSDs. The question is now more about who will succeed to develop first the lowest cost process and will take the risk of the huge initial infrastructure investment required. Going further, Logic based 3D-SOCs are to set to take-off in the 2-3 years time frame for different applications. Indeed, this "true" type of 3D-IC integration will be achieved through the progressive segregation of several layers: 3D Partitioning of embedded memories, RF, Analog and I/Os layers from the logic base chip will be achieved in the most cost effective manner by reducing overall chip size areas. We are today confident that 3D-ICs will soon show more cost effective compared to traditional SOC approaches as it will enable to partition in a cost effective manner the different functions today all integrated into large area SOC dies. Beyond cost, these 3-D chips will additionally benefits from performance improvements as interconnect length will be shortened and repeaters will be removed. This will allow the CMOS industry to "virtually" go beyond to the 32nm node in terms of chip size, cost and performance.

- We believe that different 3-D technology platforms need to be developed as they will serve different application needs and will correspond to different players in the supply chain:

- - 3-D WLP Encapsulation platform is today already in production in CMOS image sensors with via through the backside of the wafer. It will expand to Power amplifier modules as well. MEMS package are more complex as most of these applications will need a full-hermetic cavity through the use of getters and more specialized bonding technologies.

- - 3-D TSV Stack platform is being primarily developed for stacked memories and logic 3D-SOCs later on. If via-last will account for a large portion of the market, we see a clear trend towards via-first configurations and smaller vias size approaching 1-5um diameters with 500-2000 interconnects per chip typically.

- - 3-D interposer Module platform is already in very small production for several MEMS applications in order to combine the ASIC & MEMS chips together in a true WLP approach (The silicon interposer acts here in direct replacement of the organic substrate). This technology platform is likely to expand rapidly into many SiP application spaces. In most cases, the silicon 3D interposer is used as a "companion chip" module for the 3D integrated system. Benefits of such 3-D silicon interposers include outstanding intrinsic thermal properties (CTE) of the silicon package/substrate/board and the potential to scale to unlimited interconnect pitches. Furthermore, they leverage the possibility to be more and more "engineered" among time with the capability to integrate passive devices, to form cavities or even to build micro-cooling channels for cost efficient thermal management modules. More generally, 3-D silicon interposers must be low cost and may be handled or manufactured by IDM's subcontractors if the confidentiality value chain can be ensured. We do see tot

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