SUSS MicroTec Test Systems
(FWB:SMH)(GER:SMH) today announced receipt of purchase orders for test equipment
that will enable the development of next-generation integrated circuits (ICs),
including CMOS transistor scaling to the 16-nm node and beyond and the investigation
of the reliability characteristics of high-k dielectrics. The partnership with
SEMATECH, a global consortium of chipmakers, Core Wafer Systems and the College
of Nanoscale Science and Engineering (CNSE) of the University at Albany includes
advanced 300-mm wafer-level characterization systems with ProbeShield Technology
and a cryogenic probe capability system to be installed at CNSE’s world-class
Albany NanoTech Complex.
In the drive for commercialization of nanotechnology, new measurement challenges
have arisen in characterizing the latest semiconductor devices for generating
accurate transistor models, which are the building blocks of next-generation
ICs. Traditional I-V and C-V measurements are insufficient to characterize and
predict device performance and lifetime of devices and circuits in state-of-the-art
technological nodes. Moving forward, advanced and complex measurement techniques
are required, which engineers use to accurately extract important data such
as S-parameters (high-frequency measurements) and flicker-noise (1/f noise)
parameters. The choice of ProbeShield and ASUR Technologies, the most advanced
300-mm characterization system for device modeling and wafer-level reliability,
ensures that the engineering staff will remain on the cutting-edge of semiconductor
and nanotechnology.
“At SEMATECH, we are researching and developing practical solutions for
continued scaling of next-generation semiconductor technologies,” said
Dr. Gennadi Bersuker, Fellow of SEMATECH. “The test equipment from SUSS
MicroTec, in conjunction with advanced test software capabilities from Core
Wafer Systems, will enable us to characterize the new transistor processes and
designs, which increases the reliability and lifetime of electronic products.”
Additionally, the miniaturization of semiconductor devices has driven research
on the use of new materials in semiconductor devices. Much of this basic research
is carried out at cryogenic temperatures. The cryogenic probe system will enable
researchers to characterize new materials, such as high-k stacks and compound
semiconductor on silicon, at temperatures down to 4 K in a vacuum of 10-6 mbar.
The system’s unique design provides high throughput and accuracy for advanced
I-V, C-V and RF measurements up to 67 GHz.
“As leading-edge research and development at the UAlbany NanoCollege
seeks to extend CMOS transistor scaling to the 16nm node and beyond, it is increasingly
important to understand new generations of high-k materials as they are introduced
into real products,” said Richard Brilla, Vice President for Strategy,
Alliances and Consortia at CNSE. “The SUSS Cryogenic Probe System provides
a core competence within CNSE’s Albany NanoTech that will help researchers
recognize how newly developed processes can improve the desired fundamental
properties of advanced substrates, such as electron mobility. In addition, the
low-frequency noise measurement is a critical capability, as it enables us to
identify defects in advanced high-k dielectrics.”
“This is just another clear example of the SUSS MicroTec Test Division
working strategically with leading industry partners to deliver solutions valued
by those who face complex semiconductor probing and measurement challenges.”
Said Rob Carter, Vice President of Sales & Marketing for SUSS MicroTec Test
Systems. “Combined with the largest of IDM’s/Foundries who are also
embracing SUSS MicroTec Test solutions, this project will create further technological
advancements that will ensure dividends on improved processes and reliability
for our valued customer base well into the future.”