Magma Design Automation
Inc. (Nasdaq:LAVA), a provider of chip design software, today announced
that Toshiba Corporation, the world's leading supplier of semiconductors for
consumer electronics, has deployed Magma's Talus(r) IC implementation software
for developing ICs at 90-, 65- and 40-nanometer (nm) process nodes that target
multimedia, networking and printer applications, in Toshiba worldwide design
centers. Toshiba adopted Talus after an extensive evaluation that proved the
software's ability to drastically reduce turnaround time, increase designer
productivity and improve quality of results. Toshiba deployed Magma design implementation
software in Toshiba's Apex flows in 2001, and now has finished multiple designs
including 65-nm and 40-nm tapeouts using Talus through its Apex 4.0 flow.
"Toshiba has demanding delivery schedules and performance requirements,
and Magma has been instrumental in enabling us to address ever-increasing design
and market challenges," said Takashi Yoshimori, Assistant Chief Technology
Executive of SoC design, Semiconductor Company, Toshiba Corporation. "Talus
recently allowed us to reduce turnaround time drastically and improve leakage
power and area for a multi-mode SoC design with more than 10 million gates.
Based on this achievement and proven track record, we are now implementing our
90-, 65- and 40-nm designs with Talus."
"For Toshiba and its customers, reducing turnaround time is key,"
said Premal Buch, general manager of Magma's Design Implementation Business
Unit. "Toshiba's adoption of Talus firmly establishes Magma's software
as the fastest path to silicon."
Talus: The Platform for Nanometer IC Design
Magma's Talus IC implementation is a completely unified RTL-to-GDSII system
with advanced capabilities for nanometer design. To address shorter time-to-market
windows, Talus is the first implementation solution to multi-process the entire
IC design flow. Its front-end design system provides logic designers with a
fast, high-capacity, physically aware synthesis capability. Its physical design
system addresses variability and multi-mode/multi-corner complexity with new
optimization, place and route, and clock tree synthesis technology. To reduce
leakage and dynamic power, Talus also provides a complete low-power design system.
To improve manufacturability and reliability, Talus provides built-in design-for-manufacturing
(DFM) features such as redundant via and litho-aware routing for yield optimization.