Synopsys has introduced the IC Compiler-Advanced Geometry, a new version of its IC compiler, to provide design support for double-patterning technology (DPT), which serves as a pre-requisite for advanced silicon technology at 20 nm and imposes stringent restrictions on routing, placement and physical validation.
The company has worked with foundry partners and big clients to verify that IC Compiler can be used at 20 nm. The IC compiler offers physical implementation systems that are DPT-ready with high efficiency, low impact on turnaround time and conventional design measurements of speed, device area, and power.
Currently, the lithography technique that sustains IC manufacturing attains a theoretical value at the 20nm node, thus making it tough to attain very low resolution for silicon structures. A dual approach is possible. The first approach is a 20nm design, which does not have silicon-efficiency but offers a resolution below the minimum limit. Another design involves dividing into two groups of alternating structures, each having lesser resolution than the minimum but yet when joined together completely utilizes all existing silicon resources. The latter is known as double pattern technology needs a place-and-route device to precisely produce a layout where every candidate layer decomposes into two alternating patterns without affecting device area and performance.
The new version of IC Compiler is capable of formulating double patterning needs as a common coloring issue, thus preventing all possible conflicts and delivering a correct-by-construction solution that can be decomposed reliably during production. Moreover, the in-design physical verification of the IC validator has been improved to satisfy DPT standards, thus allowing IC designers to prove that target layers present in the design can be decomposed before handing-over to manufacture.
Source: http://synopsys.mediaroom.com/