Lattice Semiconductor has started the shipment of samples of its MachXO2 PLD portfolio utilizing a 2.5 x 2.5 mm 25-ball wafer level chip scale package (WLCSP). The MachXO2, developed on a low power 65-nm method featuring entrenched flash technology, can be used for applications previously not possible by programmable logic devices (PLDs).
The MachXO2 devices offer 10 times more embedded memory, 3 times more logic density and over 100 times reduction in static power when compared with earlier versions. Ultra low power and excellent PLD functionality are other features of the devices.
Mike Orr, who serves as Vice President of Product Development at Lattice Semiconductor, stated that WLCSP is an ideal packaging solution for the PLD market that requires an extremely small form factor. WLCSP has exceptional performance for thermal attributes, power management and signal integrity, he said. It is inexpensive, dependable and utilizes regular board mounting methods for easy handling and manufacturability, he added.
Lattice Semiconductor’s Director of Marketing for Silicon and Solutions, Shakeel Peera stated that the company has coupled robust packaging technologies to offer the ultra small PLDs to the programmable logic industry. The ultra-compact MachXO2 devices with extremely low power and superior functionality can be used for a totally new range of applications that are not previously possible to SRAM-based PLDs, he said. These latest MachXO2 devices will offer more options for digital logic designers working on space-constrained applications, without compromising programmability and flexibility, he added.
Source: http://www.latticesemi.com