Cadence Design Systems has reported that STMicroelectronics has used Cadence tools to tape out a 20-nm test chip, integrating customized analog and digital technologies to facilitate mixed-signal SoC design at 20 nm process node.
Engineers at Cadence and STMicroelectronics closely worked on developing technologies and implementing processes with the help of Cadence Encounter and Virtuoso platforms to facilitate design, implementation and signoff as well as in developing a SKILL-based process design kit (PDK) and foundational IP for the 20-nm process node.
This 20-nm tapeout corroborates Cadence’s dominance in providing an end-to-end mixed-signal design flow for this advance process node. As part of this partnership, STMicroelectronics has implemented the complete Cadence 20-nm flow, the associated PDK and physical IP libraries.
STMicroelectronics utilized Cadence Virtuoso Layout Suite to carry out automated layout generation in its custom IP design development, which includes foundation IP, video DAC and PLL. Designers utilized a 20-nm PDK because it provides advanced capability such as constraints, Modgens and space-based routing, thus helping them ensuring accurate results.
The Encounter Digital Implementation system enabled 20-nm physical implementation capabilities for this 20-nm test chip tapeout, dealing 20-nm process prerequisites during placement, routing and optimization.
Cadence’s Senior Vice President of Research and Development for Silicon Realization Group, Dr. Chi-Ping Hsu commented that through their partnership, STMicroelectronics and Cadence have implemented an effective process and design automation to handle the prerequisites to design complex mixed-signal SoCs.
STMicroelectronics’ Group Vice President of Technology Research and Development, Philippe Magarshack stated that the company joined forces with Cadence during the launch of the 20-nm development, and the successful tapeout of the 20-nm test chip corroborates the success of that partnership.
Source: http://www.cadence.com