Synopsys Launches Memory Test Solution for 20-Nanometer SoC Designs

Published on November 7, 2012 at 4:30 AM

Synopsys, Inc. (Nasdaq:SNPS), a global leader providing software, IP and services used to accelerate innovation in chips and electronic systems, today announced a new release of its DesignWare® STAR Memory System®, an automated pre- and post-silicon memory test, debug, diagnostic and repair solution that enables designers to improve quality of results (QoR), reduce design time, lower test costs and optimize manufacturing yield.

The latest release, targeting 20-nm- and FinFET-based designs, includes a new architecture enabling hierarchical implementation and validation of large SoC designs containing thousands of embedded memories, which can decrease the time required to implement tests while also reducing area by as much as 30 percent. In addition, the new release efficiently addresses test and repair for new memory defects seen in 20-nm processes and below such as process variation faults and resistive faults.

"With embedded memories occupying nearly 50 percent of an SoC, having a comprehensive memory test solution with built-in self-test and repair is critical to achieving optimal yield, while lowering overall costs," said Eric Esteve, IP Analyst at IPNest. "Synopsys' introduction of its next generation of the DesignWare STAR Memory System significantly improves designers' ability to detect specific memory defects and failure mechanisms that are prevalent in designs at 20 nanometers and below."

The new architecture in the STAR Memory System provides advanced memory addressing and programmable memory background patterns needed to create optimized test algorithms for detecting not only static and dynamic faults, but also process variation and resistive faults, which are more likely to occur at technology nodes of 20 nm and below. The new version also optimizes the test generation logic by storing only the unique test elements, providing significant area savings.

The STAR Memory System allows hierarchical generation and verification of the test and repair IP within the SoC while maintaining the original design hierarchy. This can speed up design and verification time while allowing reuse of existing design constraints and configuration files, reducing the overall SoC design time. The combination of these new features reduces total test and repair area by up to 30 percent compared to the previous generation product, while enabling faster design closure. These capabilities can also reduce the time required for silicon bring-up and defect analysis for yield optimization, enabling the ramp to volume production to occur in weeks rather than months.

The solution allows at-speed test and repair of high-performance processor cores by using a preconfigured test bus, which provides access to the memories inside the core in test mode. The system uses this bus to test memories and adds memory test and repair logic outside the IP core to avoid any impact on processor core performance. Designed for use with repairable and non-repairable memories for any foundry or process node, the STAR Memory System provides integration with Synopsys' DesignWare Embedded Memories by hardening the timing-critical test and repair logic within the memories, further improving performance, power and area as well as test quality.

In combination with Synopsys' comprehensive portfolio of synthesis-based test solutions including TetraMAX® ATPG and DFTMAX™ compression, DesignWare SerDes IP with built-in self-test and Yield Explorer® tool for yield analysis, the STAR Memory System provides a complete test solution suite to quickly meet overall test cost and quality goals.

"For 20-nanometer SoC designs, implementing robust, area-efficient memory test and repair IP is critical to managing manufacturing yield," said John Koeter, vice president of marketing for IP and systems at Synopsys. "The latest STAR Memory System release not only improves fault coverage and repair, but does so while reducing silicon area by almost a third, enabling engineering teams to get their 20-nanometer designs to market faster with lower manufacturing costs."

Source: http://www.synopsys.com/

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