Apr 29 2015
Uniquify today announced it developed a DDR3 intellectual property (IP) solution for Samsung Electronics' power-efficient 28nm LPP foundry process that is now in volume production for multiple product lines, including consumer and mobile applications.
The year-long project required development of DDR3 subsystem IP to deliver the highest possible performance in Samsung's 28 nanometer LPP process. In silicon, the resulting DDR3 solution was able to deliver performance that was even higher than expected by more than 10%.
Uniquify implemented the DDR3 controller, DDR3 PHY, customized to support a unique address-sharing feature for more flexibility, and DDR3 I/O tuned to the process.
"Our close technical association with Samsung makes us quite proud," says Josh Lee, chief executive officer of Uniquify, a leading high-performance semiconductor IP and system-on-chip (SoC) design, integration and manufacturing services supplier. "The results of this high-profile project demonstrate the strength of our DDR IP technology and solutions, and our flexibility and willingness to work closely with our partners to deliver solutions optimized for their specific needs. Our underlying technology and flexibility is a great advantage for us as we push the envelope in new DDR technologies such as LPDDR4 and advanced process nodes."
Today's SoC designs must be able to support DDR memory interfaces running at multi-GHz clock rates while managing read-write timing margins that are measured in picoseconds. Even a small drift in timing on the DDR interface can cause the DDR memory subsystem to fail and, as a result, the entire system fails.
Uniquify incorporates patented technology in its DDR PHY IP that counteracts the effects of timing shifts due to both static and dynamic variations caused by process, temperature and voltage. Dynamic self-calibrating logic (DSCL) tracks DDR timing at the byte level and automatically centers the sampling point in the middle of the timing window during system operation. Dynamic adaptive bit calibration (DABC) works within the byte lane to automatically adjust for any skew differences between bits. Not only do DSCL and DABC allow the DDR memory interface to be optimized for speed by maintaining the robustness of the timing interface, the Uniquify DDR IP architecture also delivers the smallest footprint and lowest power solution. In the case of the DDR3 IP developed for Samsung's 28LPP process, the combination of DSCL and DABC allowed the DDR memory performance to be improved by 10% over the required specification.
Source: http://www.uniquify.com/