Cadence Design Systems, Inc., a leader in global electronic design innovation, announced today that GLOBALFOUNDRIES has collaborated with Cadence® to provide pattern classification data for manufacturing processes of 20 and 14 nanometers.
GLOBALFOUNDRIES is using the Cadence Pattern Classification and Pattern Matching Solutions because they enable up to four times faster design for manufacturing (DFM), which is key to improving customers' silicon yield and predictability.
"We have integrated Cadence pattern classification technologies to classify yield detractors into pattern families based on pattern similarity, including inexact patterns, to maximize the efficiency of the pattern matching-based lithography signoff flow called DRC+," said Luigi Capodieci, fellow and senior director of DFM at GLOBALFOUNDRIES. "The innovative DRC+ signoff flow has been successfully used on several 32- and 28-nanometer production IC designs, and we are now using it in today's most advanced process geometries."
Cadence pattern classification technology allows GLOBALFOUNDRIES to classify hundreds of thousands of yield detractor, process hotspots, and silicon failures into easily usable pattern libraries. Cadence Pattern Search and Matching Analysis are embedded in Cadence Litho Physical Analyzer, Physical Verification System and the unified Virtuoso® custom/analog and Encounter® Digital Implementation System solutions. This offers GLOBALFOUNDRIES customers the flexibility to leverage the in-design signoff pattern matching and automatic fixing available in Encounter and Virtuoso, which correlates 100 percent with the full-chip signoff flow and has successfully been used on advanced node production chips.
For GLOBALFOUNDRIES customers using Cadence design tools, the silicon-proven DFM flow is easy to use and integrates seamlessly with Cadence custom, digital, and full-chip signoff flows. The integration of pattern matching-based DRC+ into the Virtuoso Layout Suite enables a powerful, correct-by-construction methodology and enables sophisticated avoidance and auto-fixing of bad patterns. Encounter Digital Implementation System has been able to accurately and quickly find and fix 100% of the DRC+ violations without introducing additional DRC or DRC+ violations, and has been successfully used on several 28-nanometer designs.
"DFM serves as an increasingly important link between chip development and manufacturing, and can play a huge role in silicon yield and predictability," said Chi-Ping Hsu, senior vice president, Silicon Realization Group at Cadence. "Cadence pattern classification technology helps GLOBALFOUNDRIES customers set and meet high expectations for yield, ensuring they get the highest possible return out of their complex designs. We appreciate GLOBALFOUNDRIES' commitment to use our technology at 20 and 14 nanometers and the nodes to follow."