To continue the industry's historical trend of performance scaling, SEMATECH
experts reported on integrated approaches to CMOS logic and memory device technology
and 3D TSV (through silicon via) manufacturing at the International Symposium
on VLSI Technology, System and Applications (VLSI-TSA) on April 26-28, 2010.
In a series of eight research papers, an international team of SEMATECH researchers
addressed the various challenges and process solutions for extending advanced
memory and logic technologies. The papers, selected from hundreds of submissions,
outlined leading-edge research in areas such as high-k/metal gate materials,
flash memory, and planar and non-planar CMOS technologies.
“The processes, materials, and device structures that will define next
generations of CMOS and non-CMOS technologies, and how they function when combined
as a module, is of critical importance to enhance functionality and performance
in future generations of devices,” said Raj Jammy, vice president of Materials
and Emerging Technologies. “The research that was presented at VLSI-TSA
demonstrates SEMATECH's leadership and innovative thinking in new materials,
processes and concepts that enable CMOS scaling and pave the way for emerging
In one potentially industry-changing technology, Sitaram Arkalgud, director
of SEMATECH's 3D Interconnect program, described a via-mid approach to
TSV technology on a 300 mm platform. Arkalgud discussed process development,
module integration and the overall manufacturability outlook for via–mid
TSV, a front-end process which allows a reduction in the interconnect length
as well as an increase in bandwidth between the stacked chips, resulting in
lower power, higher performance, and increased device density.
Additionally, SEMATECH front-end process technologists reported technical advances
in the following areas:
- Exploring alternative high-k dielectrics to address challenges in gate-first
and gate-last technology for the 28 nm node and beyond. SEMATECH reported
a higher performance in a silicon germanium (SiGe) P-channel MOSFETs (pFET)
when integrated into a dual channel single metal gate CMOS. In a gate-last
approach, SEMATECH results showed a low temperature process that achieves
the CMOS voltage target for both the N channel and the P channel suitable
for 20 nm generation.
- Determining that the extremely high energy and spatial resolution of synchrotron
X-ray photoemission spectroscopy (XPS) and extended X-ray absorption fine
structure (EXAFS) techniques applied to advanced hafnium-based dielectric
film systems have revealed subtle and significant chemical state and crystal
phase transitions that give rise to the mechanisms responsible for improved
- Identifying vacuum ultraviolet (VuV) reflectivity as an in-line metrology
solution for characterizing sub-nm Al2O3 and La2O3 capping layers on advanced
high-k film stacks.
- Exploring the promise of FinFETs as candidates for continuing transistor
scaling, even though measuring these devices presents challenges, particularly
for understanding the dielectric interface, since the Si body on these devices
is not available for probing. By changing from a transistor to a gated diode,
SEMATECH determined that this problem can be avoided and robust, meaningful
measurements can be obtained.
- Conducting a thorough study of TANOS structures that highlighted differences
in how the degradation of program, erase, and retention modes are dominated
by different mechanisms.
- Through a systematic evaluation of the thermal budget dependence of the
structure and property of III-V MOSFETs, demonstrating reduced external resistance
with laser anneals—a critical building block for scaling III-V MOSFETs.
- Describing experimental observations of a strained SiGe quantum well (QW)
pMOSFET, showing that it is a promising candidate for CMOS technology at 22
nm node and beyond.
- Highlighting the necessity of biaxial strain engineering to boost the performance
of FinFETs through reducing parasitic resistance as the industry scales past
the 22 nm node.
The International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA)
is sponsored by the Institute of Electrical and Electronics Engineers, or IEEE,
a leading professional association for the advancement of technology in association
with Taiwan's Industrial Technology Research Institute (ITRI). VLSI-TSA
is one of many industry forums SEMATECH uses to collaborate with scientists
and engineers from corporations, universities and other research institutions,
many of whom are research partners.