Dow Unveils Advanced SiLK Resin With Smaller Pore Size - New Technology

The Dow Chemical Company has introduced an advanced porous SiLK semiconductor dielectric resin with a significantly reduced pore size, enabling continuous physical-vapour-deposited (PVD) tantalum barriers for 65-nm semiconductor technology and beyond.

Porous SiLK Y resin, which is currently being sampled to key customers and development partners, features an average pore diameter of <2-nm and a pore size distribution range of 1- to 3-nm – the smallest closed-pore size of any commercially available interlayer dielectric (ILD) material. Porous SiLK Y resin also provides an optimized coefficient of thermal expansion (CTE) profile to enhance device reliability and ease overall material integration.

“Integrating porous dielectric materials has been a huge challenge for the industry,” said Mark McClear, global business director of the Dow Advanced Electronic Materials (AEM) business. “This leap forward in materials technology enables continuous tantalum barriers without extra process steps such as plasma treatments or ‘pore-sealing.’  In addition, our data shows the electric properties and barrier performance of porous SiLK Y resin are indistinguishable from fully dense low-k materials.”

Barrier integrity is critical for the successful integration and reliability of low-k dielectrics.  Continuous barriers prevent copper migration, which causes electrical breakdown and premature device failure. Barriers have proved to be a challenge for all porous ILDs, due to large (so-called “killer”) pores and open-cell pore morphologies.

Porous SiLK Y resin incorporates a closed-pore structure with evenly distributed pores, yielding an ultra-low-k value (k=2.2), while maintaining mechanical toughness and compatibility with conventional back-end-of-line (BEOL) unit operations, especially chemical mechanical planarization (CMP). The porous material also demonstrates a surface roughness comparable to non-porous materials, enabling the extension of cost-effective timed-etch integration schemes.

With the closed-pore morphology of porous SiLK Y resin, the sheet resistance of the tantalum barriers can be significantly reduced.  Barriers deposited on porous SiLK Y have shown up to a 90 percent improvement in sheet resistance and electrical performance compared to all previously reported porous dielectrics. “Porous SiLK Y resin enables continuous barrier coverage and yields electrical performance that matches that of non-porous ILD materials,” said McClear.

The nanoscale pore size and pore size distribution of porous SiLK Y resin were measured with on-wafer small-angle x-ray scattering (SAXS) and transmission electron microscopy (TEM) image analysis. Additionally, University of Michigan researchers independently confirmed these findings via positron annihilation lifetime spectroscopy (PALS).

Further extending the thermal expansion optimizations engineered with SiLK D resin, porous SiLK Y resin features a dramatically enhanced CTE profile. The high-temperature thermal expansion behaviour of porous SiLK Y resin is more than 50 percent lower than that of even SiLK D resin, and more than 150 percent improved relative to earlier versions of SiLK resin and other organic dielectric materials.

In the past, thermal expansion has posed a reliability challenge in the integration of organic ILD materials, as significant mismatches between the ILD and the barrier deposited upon it can cause complications and reliability concerns during thermal cycling, including metal interconnect damage, depending on the design rules used.

Because they are based on a polymer matrix, all SiLK and porous SiLK films demonstrate excellent etch, cleaning, moisture resistance, toughness and CMP compatibility with existing IC manufacturing tools.

“This dramatic minimization in pore size and CTE performance have not come at the expense of other materials properties. As the 26 partners in the SiLKnet Alliance data network have demonstrated, porous SiLK films do not suffer from via poisoning, cleaning chemistry contamination or cracking under the mechanical stresses of CMP and packaging,” said McClear. “Porous SiLK Y resin builds upon our knowledge and experience with previous SiLK resins and maintains all of these excellent properties.”

SiLK resins are a family of spin-on, low-k ILD materials that allow semiconductor manufacturers to increase chip speed and performance. First-generation SiLK resin products offer k=2.6 for both copper damascene and aluminium/tungsten processing, a k-value reduction of more than 35 percent versus conventional chemical vapour deposition (CVD) oxide dielectric films.  Dow offers a clear, extendible path to next-generation chip technologies with porous SiLK resin.

Posted 15th December 2003


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