Applied Materials and Soitec to Develop Germanium-on-Insulator Substrates - New Technology

Applied Materials, Inc. and Soitec announced a strategic agreement to jointly develop advanced germanium-on-insulator (GeOI) and other related critical Ge-based processes designed to significantly enhance transistor performance at the 45nm and beyond technology nodes. The companies will combine the power of Soitec's Smart Cut technology and engineered substrate expertise with the advanced epitaxial deposition capabilities of the Applied Centura RP Epi system to speed the development and production of these future generation substrates.

"We are pleased to join forces with industry leader Applied Materials to enable further materials innovation," said Pascal Mauberger, Soitec's chief operating officer. "Coupling Applied's epitaxial materials capability and broad equipment and technology portfolio with Soitec's successful history of pioneering and commercializing breakthrough engineered substrates allows us to drive major technical advances in transistor performance over the next three to four chip generations. This technology will be critical to leading chipmakers who are seeking a new set of transistor and substrate solutions to enable a wide range of emerging applications."

The focus of the joint program is on the development of germanium epitaxial layers that will be transferred using Soitec's patented Smart Cut technology to build the GeOI wafers. Smart Cut technology is currently used in the vast majority of advanced engineered silicon applications. Applied Materials' Centura RP Epi system uses specialized technology to deposit the full range of germanium epi films, from 100% germanium to virtually any germanium/silicon combination, enabling the optimization of a variety of silicon and Ge-based substrate designs.

According to Dr. Randhir Thakur, vice president and general manager of Applied Materials' Front End Products group, "Germanium compounds are expected to provide the foundation of many advanced materials in future chips, starting at the 45nm node. Working with Soitec, the leader in SOI (silicon-on-insulator) and other engineered substrates, we can exploit the unique capabilities of our epitaxial technology. By aligning our respective 45nm technology roadmaps, we can accelerate our shared goal of developing cost-effective 300mm GeOI manufacturing processes to enable the volume production of tomorrow's GeOI-based chips."

Germanium-based materials show great promise for future high-speed logic applications because they allow electrons to flow faster through the material, potentially speeding transistor switching by 3x to 4x over silicon. Because of bulk silicon's scaling limitations - at and beyond the 45nm chip generation - many chipmakers are evaluating engineered GeOI-type substrates to enhance device performance.

Posted 11th March 2004

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