Posted in | Nanoelectronics

Synopsys Announces 100th Successful DesignWare IP for 28-nm Processes

Synopsys announced its 100th successful DesignWare IP designed for 28-nm processes used in leading foundries. The complete 28-nm DesignWare IP line consists of PHYs for MIPI, DDR, HDMI, SATA, PCI Express, USB, and also logic libraries, embedded memories, audio codecs and data converters. In order to provide design robustness, the 28-nm DesignWare IP has been silicon-characterized in both PolySiON and High-K Metal Gate technologies across temperature, process and voltage variations.

Synopsys offers DesignWare IP solutions for designers, which can be integrated into system-on-chip (SoC) applications in a quick and effective manner. Some design aspects in its IP were modified to take care of the design requirements of the 28-nm process node for which the I/O voltages, leakage power and design rules are different when compared to 65-nm and 40-nm processes. As an example, the company carried out double the number of checks for restrictive design rule on the 28-nm IP, in comparison to the 65-nm process, to conform to the manufacturing requirements.

Synopsys used statistical design methodologies to design the 28-nm DesignWare embedded memories, and incorporated dual voltage and source biasing rails to reduce the leakage power by 70%. These features enhance the performance of SoC designs which incorporated the 28-nm DesignWare IP. The company’s Vice President of Marketing for IP and Systems, John Koeter, said that the company will provide 28-nm IP of high quality within the available timeframe for the designers, as the data collected from their user survey indicated a rise in the customers’ demand for 28-nm processes. He also said that the 28-nm DesignWare IP has been effectively designed and tested by the company consistently over a period of nearly 100 staff-years.


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