Posted in | News | Nanoelectronics

Synopsys Announces 100th Successful DesignWare IP for 28-nm Processes

Synopsys announced its 100th successful DesignWare IP designed for 28-nm processes used in leading foundries. The complete 28-nm DesignWare IP line consists of PHYs for MIPI, DDR, HDMI, SATA, PCI Express, USB, and also logic libraries, embedded memories, audio codecs and data converters. In order to provide design robustness, the 28-nm DesignWare IP has been silicon-characterized in both PolySiON and High-K Metal Gate technologies across temperature, process and voltage variations.

Synopsys offers DesignWare IP solutions for designers, which can be integrated into system-on-chip (SoC) applications in a quick and effective manner. Some design aspects in its IP were modified to take care of the design requirements of the 28-nm process node for which the I/O voltages, leakage power and design rules are different when compared to 65-nm and 40-nm processes. As an example, the company carried out double the number of checks for restrictive design rule on the 28-nm IP, in comparison to the 65-nm process, to conform to the manufacturing requirements.

Synopsys used statistical design methodologies to design the 28-nm DesignWare embedded memories, and incorporated dual voltage and source biasing rails to reduce the leakage power by 70%. These features enhance the performance of SoC designs which incorporated the 28-nm DesignWare IP. The company’s Vice President of Marketing for IP and Systems, John Koeter, said that the company will provide 28-nm IP of high quality within the available timeframe for the designers, as the data collected from their user survey indicated a rise in the customers’ demand for 28-nm processes. He also said that the 28-nm DesignWare IP has been effectively designed and tested by the company consistently over a period of nearly 100 staff-years.


Disclaimer: The views expressed here are those of the author expressed in their private capacity and do not necessarily represent the views of Limited T/A AZoNetwork the owner and operator of this website. This disclaimer forms part of the Terms and conditions of use of this website.

G.P. Thomas

Written by

G.P. Thomas

Gary graduated from the University of Manchester with a first-class honours degree in Geochemistry and a Masters in Earth Sciences. After working in the Australian mining industry, Gary decided to hang up his geology boots and turn his hand to writing. When he isn't developing topical and informative content, Gary can usually be found playing his beloved guitar, or watching Aston Villa FC snatch defeat from the jaws of victory.


Please use one of the following formats to cite this article in your essay, paper or report:

  • APA

    Synopsys, Inc.. (2019, February 11). Synopsys Announces 100th Successful DesignWare IP for 28-nm Processes. AZoNano. Retrieved on April 18, 2024 from

  • MLA

    Synopsys, Inc.. "Synopsys Announces 100th Successful DesignWare IP for 28-nm Processes". AZoNano. 18 April 2024. <>.

  • Chicago

    Synopsys, Inc.. "Synopsys Announces 100th Successful DesignWare IP for 28-nm Processes". AZoNano. (accessed April 18, 2024).

  • Harvard

    Synopsys, Inc.. 2019. Synopsys Announces 100th Successful DesignWare IP for 28-nm Processes. AZoNano, viewed 18 April 2024,

Tell Us What You Think

Do you have a review, update or anything you would like to add to this news story?

Leave your feedback
Your comment type

While we only use edited and approved content for Azthena answers, it may on occasions provide incorrect responses. Please confirm any data provided with the related suppliers or authors. We do not provide medical advice, if you search for medical information you must always consult a medical professional before acting on any information provided.

Your questions, but not your email details will be shared with OpenAI and retained for 30 days in accordance with their privacy principles.

Please do not ask questions that use sensitive or confidential information.

Read the full Terms & Conditions.