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Study Demonstrates Benefits of FD-SOI Technology for 20 and 28 nm Process Nodes

According to a joint research carried out by GLOBALFOUNDRIES, ARM. IBM, STMicroelectronics and other major semiconductors firms for producing 28 nm chips using fully depleted silicon-on-insulator (FD-SOI) process, planar semiconductor devices built on FD-SOI substrates are capable of delivering significant performance and power benefits when compared to CMOS devices fabricated on bulk-silicon substrates.

The findings also confirmed that the performance of the FD-SOI devices are capable of matching the performance assured by FinFET devices of 20 and 28 nm process technology nodes at the earliest. In the demonstration of silicon-calibrated simulations of intricate circuits comprising DDR3 memory controllers and ARM cores at the 28 nm node, the FD-SOI technology delivered superior performance over bulk CMOS technology even during the lowering of the power supply.

The FD-SOI technology delivers optimal performance equivalent to that of leaky general purpose technologies, at a leakage power and dynamic power lesser than that can be achieved by low-power technologies. The 28-nm FD-SOI circuit’s critical paths at 0.6 V were two folds faster than that of low-power technology and 50% faster than that of general purpose technology.

The FD-SOI technology consumes 40% less power by utilizing a lower power supply to achieve the equal target frequency. It allows the operation of all designs of digital devices such as SRAMS at a lower power supply. The technology also confirmed these benefits at the 20 nm node simulations.

At steady total power and based on design optimization efforts, the FD-SOI technology’s optimal performance was 12% to 30% higher than that of bulk technology specially designed for system-on-chip (SOC). It consumed 22% to 40% less power at consistent optimal operating frequency and its low-power performance was increased by 65%. The SOI Industry Consortium’s Executive Director, Horacio Mendez stated that the FD-SOI also delivers minimal production risk when compared to FinFET due to its capability to house planar designs.

Source: http://www.soiconsortium.org

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