A multiplier is an essential component of a digital system. In an article recently published in Electronics Letters, the researchers constructed an ultra-efficient, less complicated, high-speed simple multiplier based on two-bit Vedic multiplier mathematics by using a QCADesigner-E modeling environment. The proposed architecture has less area and cell count than other current structures.
Study: A novel nano-scale architecture of Vedic multiplier using majority logic in quantum-dot cellular automata technology. Image Credit: GiroScience/Shutterstock.com
Quantum-dot Cellular Automata (QCA)
Nanoscience and nanoparticles have gained popularity in recent years. At the nano-scale range, the current technologies based on transistors have physical constraints, causing degradation of characteristics in field-effect transistors, thus producing difficulties of short channels effect. To this end, substituted nanotechnologies like nanowire transistors, sin electron transistors, and QCA can overcome these shortcomings.
While the transistor-based technology uses voltage levels, QCA employs the cell’s free electron position, suggesting the importance of cells in QCA technology that is used in data transfer, connectivity, or logic computing. Based on recent improvements, QCA circuits can achieve room temperature functioning, high density, and quick switching speeds. Further, incorporating a multi-layer crossover design in the QCA circuits can reduce the number of cells, space, and complexity of the circuit.
QCA-based Vedic Multiplier
In the present study, the authors adopted a multi-layered architecture. They suggested a half-adder design with a combination of majority gates and inverter in QCA. Furthermore, a Vedic multiplication allowed bitwise multiplication, column-wise adds, and product addition. The recommended circuit includes four AND gates and two half adders.
Owing to the low complexity in the structure of half adders, the 2 × 2 Vedic multipliers were applied as a multi-layer design with low complexity by using QCADesigner-E with majority gates. The suggested QCA-based Vedic multiplier had 115 cells, that required four clock phases. Thus, the suggested architecture had reduced area and cell count compared to other current structures. Moreover, the findings from simulation studies revealed the long-term viability of the suggested design, which may be applied in constructing complicated circuits for nano-communication networks.
The Vedic multiplier was developed by using majority gates, which offered novel half-adder designs. These designs were equation-based structures, combining majority gates and a mix of the inverters.
A half subtractor creates the difference and subtracts two binary bits, X and Y, for borrowing. An overflow into a multi-digit subtraction is represented as a borrow signal. If subtraction is executed by borrowing a ‘1’, the borrow output is indicated as an AND, where XOR and an inverter were applied to construct the half subtractor circuit. The inputs to XOR gates included the AND gate’s output. The design in this experiment was made up of cells in an area of 0.02 micro square meters, and the output was generated after 0.25 clock phases.
Vedic multiplication helps in product and column-wise addition along with bitwise multiplications. The partial product was regarded as the final product’s least significant bit (LSB) after the multiplication of the LSB of Y (Y0) with that of X (X0), arranged vertically. Further, the LSB of Y (Y0) was later multiplied by the most significant bit’s (MSB) X (X1), and Y (Y1) of MSB was multiplied with X (X0) of LSB, arranged crosswise. A half adder later combined the generated (X0 × Y1+ X0 × Y1) partial products, which produced Z1 and S1 as a two-bit result, wherein the S1 of LSB was considered the final product’s second bit, and the Z1 of MSB was kept as pre carry for the subsequent step. Finally, multiplying Y (Y1) of MSB with X (X1) of MSB resulted in the creation of (X1 × Y1) partial product, and the half adder added the previously saved pre-carry. The resulting Z2 and S2 two-bit was the third and fourth bit of the product.
The quantum cost, area, delay, and throughput of the Vedic multiplier were computed by employing the QCA Designer-E. The team used a coherence vector engine and default parameters for the simulation. To ensure consistency and proper propagation in data transmission in the suggested design, the team employed the cells/ every clock zone as a design parameter.
The results from the simulation matched the values of the theoretical half-adder in QCA technology, which indicates the robustness of the proposed design. The circuit was made up of 16 cells with 0.25 clock phases and a 0.02-micrometer surface area. The QCA technology Vedic multiplier generally includes two half-adders and majority gates. However, this experiment included only 115 QCA normal cells. Furthermore, the energy dissipation was evaluated by utilizing QCADesigner-E in QCA technology. Consequently, the Vedic multiplier circuit’s energy dissipation was also evaluated by employing QCADesigner-E.
In conclusion, nanotechnology has led to recent advances in nanoelectronic circuits. Due to its higher speed and low power consumption, QCA serves as a reliable alternative to transistor-based technology. Through this study, the researchers reported a strategy to construct Vedic multipliers with cell-interaction QCA structures.
The authors were successful in designing and simulating a half-adder circuit with a QCADesigner-E modeling environment and constructed a 2 X 2 Vedic multiplier circuit. The team compared the suggested component’s performance with the other standard designs concerning area, cell count, latency, and quantum cost.
Huang, J. and Lale, S. (2022), A novel nano-scale architecture of Vedic multiplier using majority logic in quantum-dot cellular automata technology. Electronics Letters.https://ietresearch.onlinelibrary.wiley.com/doi/10.1049/ell2.12552
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