Javelin Design Automation, the leading provider of PathFinding solutions, announces a revolutionary solution for the rapid design exploration and optimization of three dimensional stacked ICs (3D SIC). Developed in close collaboration with IMEC, Europe's leading independent nanoelectronics research center, and Qualcomm, a partner in IMEC's 3D integration program, 3D PathFinding extends the Javelin PathFinding methodology and j360 Silicon PathFinder™ platform to support virtual chip design for co-optimization of system design and 3D interconnect-packaging technologies. Designers of 3D ICs are now empowered to rapidly explore many potential 3D design implementations for their technical value propositions, and to identify and mitigate risks-benefits and optimize value.
3D SIC design is an emerging and rapidly adopted methodology for advanced semiconductor companies. To support PathFinding for 3D technologies, the joint team developed a detailed 3D flow that provides accurate performance/power/cost estimates for a 3D stack. With turnaround times of a few hours or days, designers can evaluate and optimize their system and micro-architecture to best exploit 3D technology options; and silicon process engineers can fine-tune their technology to the system architecture specs. This 3D PathFinding leverages Javelin's newly announced j360 Silicon Pathfinder™ platform with enhanced PathFinding technology for fast physical design prototyping of multi-stack silicon.
Pol Marchal, principal scientist of IMEC, stated, “Javelin's Silicon PathFinder™ 3D allows us to assess the impact of various 3D interconnect strategies throughout the IC design and fabrication process, and to adapt our technology to our partners' specs.”
“We validated and used the PathFinding flow on an IMEC 3D case-study to quantify how various implementations of 3D interconnect technologies resolve the DDR2 DRAM bottleneck in an AVC H.264 encoder to achieve HD1080 quality for smart-phone applications,” said Roger Carpenter, CTO of Javelin. “The PathFinding results indicate close to 10 times decrease in dynamic interconnect power of the IO interface using 3D interconnect technologies, subsequently allowing the bus-width to increase by 16 times in 3D implementation, without exceeding the power of the original SIP implementation. This sample design case shows how TSV technology can remove the bottleneck between processor and memory”.
"We believe PathFinding is critical to the success of 3D integration technology and we are excited to work with Javelin in this area;" said Luc Van den hove, chief operation officer at IMEC. "We are confident that strong industry collaboration among foundries, IDMs, fabless companies, EDA vendors, packaging and assembly companies, and equipment suppliers within our 3D integration research program at IMEC will advance the development of innovative 3D products."
"Three-dimensional design will allow Qualcomm to offer superior features and performance in our products;" said Jim Clifford, senior VP and general manager, Qualcomm CDMA technologies.
“Customers with high-volume applications drive standardization and cost-effectiveness of innovative technologies;” said Diana Feng Raggett, CEO and co-founder of Javelin. “Javelin is pleased to be working collaboratively with Qualcomm and IMEC to accelerate the use and deployment of such disruptive, innovative technologies, and to provide a design methodology and commercial design platform that also enables other standards-based specialized tools to contribute to a full solution faster than ever before.”