Posted in | Nanoelectronics

STMicroelectronics and Synopsys Develop 20-nm Technology Demonstrator Test Chip

Synopsys, a company specializing in IP and software for semiconductor production, verification and design, has announced its research and development partnership with STMicroelectronics (ST) in the development of ST’s first test chip that demonstrates its 20-nm process technology.

International Semiconductor Development Alliance (ISDA) is the co-developer of the technology. This tapeout paves the way for the development of a detailed design solution for system-on-chip (SoC) integrated circuits (ICs) by utilizing the 20-nm process technology.

For the past one year, the researchers of Synopsys and ST jointly worked in various areas including design rule checking (DRC), parasitic extraction, complex routing coding and optimization of standard-cell library routability to create the building blocks for the 20-nm design environment.

The Group Vice President for ST Technology Research and Development, Philippe Magarshack stated that the company has worked in close collaboration with Synopsys to enable the readiness of important components in its 20-nm design flow.

According to Antun Domic, who serves as SVP and General Manager of Implementation Group at Synopsys, the latest breakthrough in 20-nm design flow demonstrates the company’s capability to offer critical components to fulfill the requirements of the 20-nm transition. He added that they would continue their collaboration with ST to implement their 20nm design and create a production-ready environment.


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