Editorial Feature

Breaking Down the Issues of Scaling Down Semiconductor Devices

Semiconductor chips have been getting smaller and smaller every year since the 1960s, with double the number of transistors fitting into the same chip space each year following the predicted trajectory of Moore’s Law. However, there may be a lower limit for semiconductor downscaling that we are beginning to approach.

Predictable Downscaling: Moore's Law

In 1965, Intel co-founder Gordon Moore noted that the number of transistors on a semiconductor (CMOS) chip was going to double every two years. This observation has come to be known as Moore's Law, and it has been well-supported in the semiconductor industry for over half a century.

Semiconductor downscaling has had a profound impact on the world. It has enabled the development of smaller, faster, and more powerful computers, which have, in turn, led to the development of new technologies such as the internet and mobile phones.

CMOS technology has followed Moore's law for 50 years, doubling the number of transistors on a chip every two years. This has led to significant improvements in performance, power, and density.

The main driver of this scaling has been the reduction in gate length. As gate lengths have decreased, the speed and power of transistors have increased.

However, as gate lengths approach atomic dimensions, it becomes increasingly difficult to reduce them further. This is where new technologies such as FinFETs and 3D transistors come in.

FinFETs use a fin-like structure to control the flow of current, while 3D transistors stack multiple layers of transistors on top of each other. These technologies allow for further scaling without the same limitations as planar transistors.

Developing these new technologies is essential to the continued success of the semiconductor industry. They will allow for the continued development of faster, smaller, and more powerful chips.

Is Moore’s Law Slowing Down?

The physical limits of CMOS technology are approaching, and the economic constraints of manufacturing 5 nm chips are formidable.

Despite these challenges, CMOS technology has survived and thrived for decades, and it is likely to continue to do so for some time. The development of new technologies, such as multi-gate FETs, will allow for the continued development of faster, smaller, and more powerful chips.

However, the end of Moore's Law is inevitable. The ultimate limit of CMOS scaling was predicted almost immediately after the technology was invented, and there are a number of technological and economic factors that will eventually prevent further scaling.

The main limitation of CMOS technology is the short-channel effect (SCE). As the gate length of a transistor decreases, the SCE becomes more pronounced. This effect causes the transistor to lose current, which reduces its performance.

There are a number of ways to mitigate the SCE, but they all have trade-offs. One way is to use a tri-gate (FinFET) structure. The FinFET structure helps to reduce the SCE by increasing the channel length of the transistor.

Another way to mitigate the SCE is to use a high-k dielectric. The high-k dielectric helps to reduce the SCE by increasing the effective oxide thickness of the transistor.

The use of FinFETs and high-k dielectrics has allowed CMOS technology to continue to scale for some time. However, these technologies are not without their limitations. For example, the FinFET structure is more difficult to manufacture than the planar structure and the high-k dielectric is also more expensive than the traditional oxide dielectric.

These limitations will eventually prevent CMOS technology from scaling any further. The ultimate limit of CMOS scaling is predicted to be around 2 nm. At this point, CMOS technology will no longer be able to scale any further. This will mark the end of Moore's Law.

Alternative Approaches to Downscaling Semiconductors

Recently, researchers writing in the scientific journal Applied Physics Letters outline three possibilities for the industry after the thermal fluctuation limit is reached and the density of FETs will be impossible or impractical to increase for room temperature operation.

The three options are:

  • Accept the end of Moore's Law and concentrate efforts on reducing power dissipation with adiabatic or reversible computing.
  • Use non-FET alternatives such as memristors, superconducting logic, etc.
  • Continue Moore's Law using single-electron transistors.

The first option is to accept that Moore's Law is no longer possible and to focus on reducing power dissipation. This can be done by using adiabatic or reversible computing. Adiabatic computing is a type of computing that uses energy that is stored in the system itself, rather than being input from an external source. Reversible computing is a type of computing that is able to undo any operation that it has performed. Both of these types of computing are more efficient than traditional computing, which could help to reduce power consumption.

The second option is to use non-FET alternatives such as memristors, superconducting logic, and so on. Memristors are a type of memory device that can store information based on the resistance of the device. Superconducting logic is a type of logic that uses superconducting materials to perform calculations. Both of these technologies are still in their early stages of development, but they have the potential to be more efficient than traditional FETs.

The third option is to continue Moore's Law using single-electron transistors. Single-electron transistors are a type of transistor that can switch using a single electron. This makes them much smaller and faster than traditional FETs. However, they are also much more difficult to manufacture.

The three options are all valid ways to continue to advance the semiconductor industry. However, it is not clear which option will be the most successful. The future of the semiconductor industry will depend on the development of new technologies and the continued innovation of existing technologies.

Semiconductors in Nanotechnology - How Does Getting Smaller Benefit Them?

References and Further Reading

Arutchelvan, G., et al (2021). Impact of device scaling on the electrical properties of MoS2 field-effect transistors. Scientific Reports. doi.org/10.1038/s41598-021-85968-y.

Hughes, A. (2021). What is Moore’s Law and is it still relevant today? [Online] BBC Science Focus. Available at: https://sciencefocus.com/future-technology/moores-law/ 

Mamaluy, D., and X. Gao (2015). The fundamental downscaling limit of field effect transistors. Applied Physics Letters. doi.org/10.1063/1.4919871.

Ratnesh, R.K., et al (2021). Advancement and challenges in MOSFET scaling. Materials Science in Semiconductor Processing. doi.org/10.1016/j.mssp.2021.106002.

Disclaimer: The views expressed here are those of the author expressed in their private capacity and do not necessarily represent the views of AZoM.com Limited T/A AZoNetwork the owner and operator of this website. This disclaimer forms part of the Terms and conditions of use of this website.

Ben Pilkington

Written by

Ben Pilkington

Ben Pilkington is a freelance writer who is interested in society and technology. He enjoys learning how the latest scientific developments can affect us and imagining what will be possible in the future. Since completing graduate studies at Oxford University in 2016, Ben has reported on developments in computer software, the UK technology industry, digital rights and privacy, industrial automation, IoT, AI, additive manufacturing, sustainability, and clean technology.


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