Posted in | Nanoelectronics

EUR 14.5m for the Development of Powerful and Efficient Electronic Devices

Electronic equipment makes our everyday routine much easier - in our jobs as well as in our leisure time. Within the DECISIF project, scientific and industrial cooperation partners want to explore the potential of "strained silicon" in order to manufacture even more powerful and energy-saving devices for laptops, mobile phones and MP3-players.

DECISIF is a milestone for the future production of more powerful microprocessors and memories with lower energy consumption resulting in extended operating time.

The Federal Ministry of Education and Science (BMBF) granted EUR 8.1m for DECISIF (DEvice and CIrcuit performance boosted through SIlicon material Fabrication). Another EUR 6.4m will be contributed by the project partners GLOBALFOUNDRIES Dresden, Siltronic AG, AIXTRON AG, Research Center Jülich as well as the Max Planck Institute of Microstructure Physics. There will also be collaboration with French partners STMicroelectronics, SOITEC and LETI within the scope of the EU-project Medea. The project is coordinated by Prof. Siegfried Mantl of Research Center Jülich.

A technique patented by the Research Center Jülich will be used amongst others to fabricate strained silicon with already mentioned favorable properties. The crystal lattice of silicon is expanded by mechanical strain to change the electrical properties of silicon: the charge carriers are able to move significantly faster through the transistor, the potential switching frequency increases and power consumption decreases. This clears the way for more powerful and at the same time even smaller transistors. Properties of (globally) strained silicon will be combined with new techniques to create locally strained silicon to reach an exceptionally high mobility of the charge carrier within transistors. To achieve this goal nano structuring will be applied.

DECISIF will build a bridge from fundamental research of strained silicon to almost production-ready process. Combining the new strained silicon and the existing silicon-on-insulator technique a new material generation on industry-compatible 300 mm wafers will be developed. These wafers will provide the base for future device technologies and transistors with up to 22 nm minimum geometry.

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