Mentor Graphics Corporation (NASDAQ: MENT), a world leader in electronic hardware and software design solutions, today announced that its silicon test and diagnosis suite has been validated by UMC, a world leading semiconductor foundry, for use in its 65 and 40 nanometer reference flows. The foundation of this comprehensive silicon test flow is the TestKompress® automated test pattern generation (ATPG) solution for achieving high test quality with the lowest test cost. Complementing this scan test solution are Mentor’s MBISTArchitect™ for memory built-in self test (BIST), the BSDArchitect™ 1149.1-compatible boundary scan tool, and the YieldAssist™ failure diagnosis and yield monitoring tools.
“Mentor provides a very thorough testing solution for our 65 and 40nm processes,” said Stephen Fu, IP Development & Design Support Division Director at UMC. “Mentor’s test tools provide the complete manufacturing test flow that our customers require. With this flow we are able to provide them with test tools that match the advanced technology provided by our 65 and 40 nanometer process nodes. This takes the guesswork out of implementing a thorough manufacturing test.”
Complete Testing Flow Provides Advanced Testing Capabilities
The UMC flow provides a range of advanced capabilities addressing new requirements in testing advanced IC devices. The TestKompress product provides highly compressed test patterns supporting a wide variety of fault models including stuck-at, transition, multiple detect, and timing-aware delay. Power-aware features in the TestKompress product adjust test patterns to reduce total power dissipation during testing and to keep maximum power under a user-specified threshold.
The MBISTArchitect tool automates the process of providing at-speed testing of multiple instances of memory, while keeping area overhead to a minimum. The BSDArchitect tool is used for inserting boundary scan and TAP control for the memory BIST. The YieldAssist tools enable rapid diagnosis of failing devices to identify the location and type of defects, keeping IC yields high.
“Our complete set of silicon test tools are targeted at advanced IC technologies such as the 65 and 45 nanometer processes offered by UMC,” said Joe Sawicki, Vice President and General Manager of the Design-to-Silicon division at Mentor Graphics. “The UMC Reference Flow means that customers will have a fully verified test flow that can be applied to a wide variety of devices.”