Posted in | Nanofabrication

New Encapsulated Wafer Level Chip Scale Package from STATS ChipPAC

STATS ChipPAC Ltd. ("STATS ChipPAC" or the "Company"), a leading provider of advanced semiconductor packaging and test services, today introduced encapsulated Wafer Level Chip Scale Package (eWLCSP™), an innovative packaging technology that raises the industry standard of durability for Wafer Level Chip Scale Packaging (WLCSP).

WLCSP is one of the fastest growing segments in the semiconductor industry driven by mobile electronics that require compact, high performance packages. Although WLCSP is considered a mature technology, there is now an increased sensitivity in the semiconductor industry to reduce the possibility of damage to the package during the surface mount technology (SMT) process. As the industry transitions to more advanced silicon node products, the exposed die that is inherent in the WLCSP design becomes more of a concern due to the fragile dielectric layers.

"WLCSP is a bare die package that is constantly exposed to potential cracking, chipping and handling damages before or during the SMT process. This is particularly true for advanced node products where the die is very thin and dielectric layers are extremely fragile," said Dr. Han Byung Joon, Executive Vice President and Chief Technology Officer, STATS ChipPAC. "As mobile device manufacturers tighten their technical specifications to reach new levels of reliability in their products, the industry will see more stringent component level and board level reliability (BLR) requirements. eWLCSP™ is a robust packaging solution that cost effectively addresses the increased durability requirements for our customers in advanced silicon nodes down to 28nm."

eWLCSP™ features a thin protective coating on the four sidewalls of the die, achieving increased durability and reliability within the standard WLCSP size specification. The significant benefit of encapsulation is the light and mechanical protection for the bare die. The protective layer also safeguards the silicon during socket insertion for test. eWLCSP delivers electrical performance that is equivalent to standard WLCSP with proven results in component level reliability (CLR), temperature cycle on board (TCoB) and drop test.

The encapsulation advantages in eWLCSP are the result of STATS ChipPAC's new FlexLine™ manufacturing method. FlexLine™ is an innovative approach to wafer level manufacturing that seamlessly processes multiple silicon wafer diameters in the same manufacturing line, delivering unprecedented flexibility in producing both fan-out and fan-in packages. Flexline™ is based on STATS ChipPAC's well established, high volume manufacturing process for fan-out wafer level packaging that provides the ability to scale a device to larger panel sizes for a compelling cost reduction compared to conventional wafer level packaging methods. The FlexLine™ process has been qualified at advanced silicon nodes down to 28nm, ball pitches down to 0.40mm and body sizes as small as 2.5x2.5mm.

Dr. Han continued, "FlexLine is a strong manufacturing platform that enables unique technology enhancements such as eWLCSP and a cost effective manufacturing approach to wafer level packaging. Using the FlexLine method, 200mm incoming wafers can be reconstituted into 300mm or larger panel sizes, providing customers with significant per unit cost reduction as the panel size increases. In addition, a conventional WLCSP can be converted to eWLCSP without any silicon design change required, regardless of the current silicon wafer diameter."

STATS ChipPAC will be presenting on eWLCSP™ and other innovations in wafer level technology, Through Silicon Via (TSV) and advanced flip chip interconnect at the Electronic Components and Technology Conference that is being held May 27th to May 30th, 2014 in Orlando, Florida.


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